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CYNSE70128
CYNSE70128 Network Search Engine
Cypress Semiconductor Corporation Document #: 38-02040 Rev. *F
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 28, 2005
CYNSE70128
CONTENTS 1.0 OVERVIEW ...................................................................................................................................... 9 2.0 FEATURES ...................................................................................................................................... 9 3.0 FUNCTIONAL DESCRIPTION ....................................................................................................... 10 3.1 Command Bus and DQ Bus ...................................................................................................... 10 3.2 Database Entry (Data Array and Mask Array) .......................................................................... 10 3.3 Arbitration Logic ........................................................................................................................ 11 3.4 Pipeline and SRAM Control ...................................................................................................... 11 3.5 Full Logic ................................................................................................................................... 11 4.0 SIGNAL DESCRIPTIONS .............................................................................................................. 11 5.0 CLOCKS.......................................................................................................................................... 13 6.0 PHASE-LOCK LOOP USAGE ....................................................................................................... 15 7.0 REGISTERS ................................................................................................................................... 15 7.1 Comparand Registers ............................................................................................................... 15 7.2 Mask Registers ......................................................................................................................... 16 7.3 Search Successful Registers (SSR[0:7]) .................................................................................. 16 7.4 Command Register ................................................................................................................... 17 7.5 Information Register .................................................................................................................. 18 7.6 Read Burst Address Register ................................................................................................... 18 7.7 Write Burst Address Register Description ................................................................................. 19 7.8 NFA Register ............................................................................................................................ 19 8.0 NSE ARCHITECTURE AND OPERATION OVERVIEW ............................................................... 19 9.0 DATA AND MASK ADDRESSING ................................................................................................ 21 10.0 COMMANDS ................................................................................................................................ 21 10.1 Command Codes .................................................................................................................... 21 10.2 Commands and Command Parameters ................................................................................. 22 10.3 Read Command ...................................................................................................................... 22 10.4 Write Command ...................................................................................................................... 25 10.5 Parallel Write ........................................................................................................................... 27 10.6 Search Command ................................................................................................................... 27
10.6.1 72-bit Search on Tables Configured as x72 Using a Single CYNSE70128 Device ...................... 27 10.6.2 72-bit Search on Tables Configured as x72 Using up to Eight CYNSE70128 Devices ................ 30 10.6.3 72-bit Search on Tables Configured as x72 Using up to 31 CYNSE70128 Devices .................... 36 10.6.4 144-bit Search on Tables Configured as x144 Using a Single CYNSE70128 Device .................. 51 10.6.5 144-bit Search on Tables Configured as x144 Using up to Eight CYNSE70128 Devices ............ 53 10.6.6 144-bit Search on Tables Configured as x144 Using up to 31 CYNSE70128 Devices ................ 59 10.6.7 288-bit Search on Tables Configured as x288 Using a Single CYNSE70128 Device .................. 74 10.6.8 288-bit Search on Tables Configured as x288 Using up to Eight CYNSE70128 Devices ............ 76 10.6.9 288-bit Search on Tables Configured as x288 Using up to 31 CYNSE70128 Devices ................ 82 10.6.10 Mixed-Size Searches on Tables Configured with Different Widths Using a CYNSE70128 with CFG_L LOW ............................................................................................................................................ 97 10.6.11 Mixed-Size Searches on Tables Configured to Different Widths Using a CYNSE70128 with CFG_L HIGH ........................................................................................................................................................ 98
10.7 LRAM and LDEV Description .................................................................................................. 98 10.8 Learn Command ..................................................................................................................... 98
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CYNSE70128
TABLE OF CONTENTS (continued) 11.0 DEPTH-CASCADING ................................................................................................................. 102 11.1 Depth-Cascading up to Eight Devices (One Block) .............................................................. 102 11.2 Depth-Cascading up to 31 Devices (Four Blocks) ................................................................ 103 11.3 Depth-Cascading for a FULL Signal ..................................................................................... 104 12.0 SRAM ADDRESSING ................................................................................................................ 105 12.1 Generating an SRAM BUS Address ..................................................................................... 106 12.2 SRAM PIO Access ................................................................................................................ 106 12.3 SRAM Read with a Table of One Device .............................................................................. 106 12.4 SRAM Read with a Table of up to Eight Devices .................................................................. 107 12.5 SRAM Read with a Table of up to 31 Devices ...................................................................... 110 12.6 SRAM Write with a Table of One Device .............................................................................. 113 12.7 SRAM Write with a Table of up to Eight Devices .................................................................. 114 12.8 SRAM Write with Table(s) of up to 31 Devices ..................................................................... 117 12.9 Timing Sequences for Back-to-Back searches ...................................................................... 120 13.0 POWER ...................................................................................................................................... 122 13.1 Power-up Sequence ............................................................................................................. 122 13.2 Power Consumption .............................................................................................................. 123 14.0 APPLICATION ........................................................................................................................... 124 15.0 JTAG (1149.1) TESTING ........................................................................................................... 124 16.0 ELECTRICAL SPECIFICATIONS .............................................................................................. 125 17.0 AC TIMING WAVEFORMS ........................................................................................................ 126 17.1 Special Note for MULTI_HIT Function on the CYNSE70128 ................................................ 129 18.0 PINOUT DESCRIPTION ............................................................................................................. 130 19.0 ORDERING INFORMATION ...................................................................................................... 135 20.0 PACKAGE DIAGRAM ................................................................................................................ 136
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CYNSE70128
LIST OF FIGURES Figure 5-1. CYNSE70128 Clocks (CLK2X and PHS_L) ........................................................................ 13 Figure 5-2. CYNSE70128 Clocks (CLK1X) ........................................................................................... 13 Figure 5-3. CYNSE70128 Clocks for All Timing Diagrams .................................................................... 14 Figure 7-1. Comparand-Register Selection during Search and Learn Instructions ............................... 15 Figure 7-2. Addressing the Global Mask Register Array ....................................................................... 16 Figure 8-1. CYNSE70128 Database Width Configuration ..................................................................... 19 Figure 8-2. Multiwidth Database Configurations Example ..................................................................... 21 Figure 9-1. Addressing the CYNSE70128 Data and Mask Arrays ........................................................ 21 Figure 10-1. Single-Location Read Cycle Timing .................................................................................. 23 Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4) ....................................................... 24 Figure 10-3. Single Write Cycle Timing ................................................................................................. 25 Figure 10-4. Burst Write of the Data and Mask Arrays (BLEN = 4) ....................................................... 26 Figure 10-5. Timing Diagram for 72-bit Search in x72 Table (One Device)........................................... 28 Figure 10-6. Hardware Diagram for a Table with One Device............................................................... 28 Figure 10-7. x72 Table with One Device ............................................................................................... 29 Figure 10-8. Hardware Diagram for a Table with Eight Devices............................................................ 31 Figure 10-9. Timing Diagram for 72-bit Search Device Number 0......................................................... 32 Figure 10-10. Timing Diagram for 72-bit Search Device Number 1....................................................... 33 Figure 10-11. Timing Diagram for 72-bit Search Device Number 7 (Last Device) ................................ 34 Figure 10-12. x72 Table with Eight Devices .......................................................................................... 35 Figure 10-13. Hardware Diagram for a Table with 31 Devices .............................................................. 37 Figure 10-14. Hardware Diagram for a Block of up to Eight Devices .................................................... 38 Figure 10-15. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ................. 39 Figure 10-16. Timing Diagram for Each Device Above the Winning Device in Block Number 1 ........... 40 Figure 10-17. Timing Diagram for Globally Winning Device in Block Number 1 ................................... 41 Figure 10-18. Timing Diagram for Devices Below the Winning Device in Block Number 1 ................... 42 Figure 10-19. Timing Diagram for Devices Above the Winning Device in Block Number 2 .................. 43 Figure 10-20. Timing Diagram for Globally Winning Device in Block Number 2 ................................... 44 Figure 10-21. Timing Diagram for Devices Below the Winning Device in Block Number 2 ................... 45 Figure 10-22. Timing Diagram for Devices Above the Winning Device in Block Number 3 .................. 46 Figure 10-23. Timing Diagram for Globally Winning Device in Block Number 3 ................................... 47 Figure 10-24. Timing Diagram for Devices Below the Winning Device in Block Number 3 (Except the Last Device [Device 30])..................................................................................................... 48 Figure 10-25. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in Depth-Cascaded Table)................................................................................................... 49 Figure 10-26. x72 Table with 31 Devices .............................................................................................. 50 Figure 10-27. Timing Diagram for 144-bit Search (One Device) ........................................................... 51 Figure 10-28. Hardware Diagram for a Table With One Device ............................................................ 51 Figure 10-29. x144 Table with One Device ........................................................................................... 52 Figure 10-30. Hardware Diagram for a Table with Eight Devices.......................................................... 54 Figure 10-31. Timing Diagram for 144-bit Search Device Number 0..................................................... 55 Figure 10-32. Timing Diagram for 144-bit Search Device Number 1..................................................... 56 Figure 10-33. Timing Diagram for 144-bit Search Device Number 7 (Last Device) .............................. 57 Figure 10-34. x144 Table with Eight Devices ........................................................................................ 58 Figure 10-35. Hardware Diagram for a Table with 31 Devices .............................................................. 60 Figure 10-36. Hardware Diagram for a Block of up to Eight Devices .................................................... 61 Figure 10-37. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ................. 62 Figure 10-38. Timing Diagram for Each Device Above the Winning Device in Block Number 1 ........... 63 Figure 10-39. Timing Diagram for Globally Winning Device in Block Number 1 ................................... 64
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CYNSE70128
LIST OF FIGURES (continued) Figure 10-40. Timing Diagram for Devices Below the Winning Device in Block Number 1 ................... 65 Figure 10-41. Timing Diagram for Devices Above the Winning Device in Block Number 2 .................. 66 Figure 10-42. Timing Diagram for Globally Winning Device in Block Number 2 ................................... 67 Figure 10-43. Timing Diagram for Devices Below the Winning Device in Block Number 2 ................... 68 Figure 10-44. Timing Diagram for Devices Above the Winning Device in Block Number 3 .................. 69 Figure 10-45. Timing Diagram for Globally Winning Device in Block Number 3 ................................... 70 Figure 10-46. Timing Diagram for Devices Below the Winning Device in Block Number 3 Except Device 30 (the Last Device)....................................................................................................... 71 Figure 10-47. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in Depth-Cascaded Table)..................................................................................................................... 72 Figure 10-48. x144 Table with 31 Devices ............................................................................................ 73 Figure 10-49. Timing Diagram for 288-bit Search (One Device) ........................................................... 74 Figure 10-50. Hardware Diagram for a Table with One Device ............................................................. 75 Figure 10-51. x288 Table with One Device ........................................................................................... 75 Figure 10-52. Hardware Diagram for a Table with Eight Devices.......................................................... 77 Figure 10-53. Timing Diagram for 288-bit Search Device Number 0..................................................... 78 Figure 10-54. Timing Diagram for 288-bit Search Device Number 1..................................................... 79 Figure 10-55. Timing Diagram for 288-bit Search Device Number 7 (Last Device) .............................. 80 Figure 10-56. x288 Table with Eight Devices ........................................................................................ 81 Figure 10-57. Hardware Diagram for a Table with 31 Devices .............................................................. 83 Figure 10-58. Hardware Diagram for a Block of up to Eight Devices .................................................... 84 Figure 10-59. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ................. 85 Figure 10-60. Timing Diagram for Each Device Above the Winning Device in Block Number 1 ........... 86 Figure 10-61. Timing Diagram for Globally Winning Device in Block Number 1 ................................... 87 Figure 10-62. Timing Diagram for Devices Below the Winning Device in Block Number 1 ................... 88 Figure 10-63. Timing Diagram for Devices Above the Winning Device in Block Number 2 .................. 89 Figure 10-64. Timing Diagram for Globally Winning Device in Block Number 2 ................................... 90 Figure 10-65. Timing Diagram for Devices Below the Winning Device in Block Number 2 ................... 91 Figure 10-66. Timing Diagram for Devices Above the Winning Device in Block Number 3 .................. 92 Figure 10-67. Timing Diagram for Globally Winning Device in Block Number 3 ................................... 93 Figure 10-68. Timing Diagram for Devices Below the Winning Device in Block Number 3 Except Device 30 (the Last Device)....................................................................................................... 94 Figure 10-69. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table)............ 95 Figure 10-70. x288 Table with 31 Devices ............................................................................................ 96 Figure 10-71. Timing Diagram for Mixed Search (One Device)............................................................. 97 Figure 10-72. Multiwidth Configurations Example ................................................................................. 98 Figure 10-73. Timing Diagram of Learn (TLSZ = 00)............................................................................. 99 Figure 10-74. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01]).............................. 100 Figure 10-75. Timing Diagram of Learn on Device Number 7 (TLSZ = 01)......................................... 101 Figure 11-1. Depth-Cascading to Form a Single Block ....................................................................... 103 Figure 11-2. Depth-Cascading Four Blocks......................................................................................... 104 Figure 11-3. FULL Generation in a Cascaded Table........................................................................... 105 Figure 12-1. SRAM Read Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)........................... 107 Figure 12-2. Table of a Block of Eight Devices.................................................................................... 108 Figure 12-3. SRAM Read Through Device Number 0 in a Block of Eight Devices.............................. 109 Figure 12-4. SRAM Read Timing for Device Number 7 in a Block of Eight Devices ........................... 110 Figure 12-5. Table of 31 Devices Made of Four Blocks....................................................................... 111 Figure 12-6. SRAM Read Through Device Number 0 in a Block of 31 Devices (Device Number 0 Timing)................................................................................................................... 112
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CYNSE70128
LIST OF FIGURES (continued) Figure 12-7. SRAM Read Through Device Number 0 in a Block of 31 Devices (Device Number 30 Timing)................................................................................................................. 113 Figure 12-8. SRAM Write Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1) ........................... 114 Figure 12-9. Table of a Block of Eight Devices.................................................................................... 115 Figure 12-10. SRAM Write Through Device Number 0 in a Block of Eight Devices ............................ 116 Figure 12-11. SRAM Write Timing for Device Number 7 in a Block of Eight Devices ......................... 117 Figure 12-12. Table of 31 Devices (Four Blocks) ................................................................................ 118 Figure 12-13. SRAM Write Through Device Number 0 in a Bank of 31 Devices (Device 0 Timing) ... 119 Figure 12-14. SRAM Write Through Device Number 0 in a Bank of 31 CYNSE70128 Devices (Device Number 30 Timing)................................................................................................................. 120 Figure 13-1. Power-up Sequence (CLK2x).......................................................................................... 121 Figure 13-2. Power Consumption of CYNSE70128............................................................................. 122 Figure 14-1. Sample Switch/Router Using the CYNSE70128 Device ................................................. 123 Figure 17-1. Input Wave Form for CYNSE70128 ................................................................................ 127 Figure 17-2. Output Load for CYNSE70128 ........................................................................................ 127 Figure 17-3. I/O Output Load Equivalent for CYNSE70128 ................................................................ 127 Figure 17-4. AC Timing Waveforms with CLK2X................................................................................. 128 Figure 17-5. AC Timing Waveforms with CLK1X................................................................................. 129 Figure 18-1. Pinout Diagram................................................................................................................ 130 Figure 20-1. 388-lead Ball Grid Array (35 x 35 x 2.33 mm) BG388..................................................... 136
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CYNSE70128
LIST OF TABLES Table 4-1. CYNSE70128 Signal Description ........................................................................................ 11 Table 7-1. Register Overview ............................................................................................................... 15 Table 7-2. Search Successful Register Description .............................................................................16 Table 7-3. Command Register Description ........................................................................................... 17 Table 7-4. Information Register Description ......................................................................................... 18 Table 7-5. Read Burst Register Description ......................................................................................... 18 Table 7-6. Write Burst Register Description ......................................................................................... 19 Table 7-7. NFA Register ....................................................................................................................... 19 Table 8-1. Bit Position Match ................................................................................................................ 20 Table 10-1. Command Codes ............................................................................................................... 22 Table 10-2. Command Parameters ...................................................................................................... 22 Table 10-3. Read Command Parameters ............................................................................................. 23 Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM ........................................... 23 Table 10-5. Read Address Format for Internal Registers ..................................................................... 24 Table 10-6. Read Address Format for Data and Mask Arrays .............................................................. 25 Table 10-7. Write Address Format for Data Array, Mask Array or SRAM (Single Write) ...................... 26 Table 10-8. Write Address Format for Internal Registers ..................................................................... 26 Table 10-9. Write Address Format for Data and Mask Array (Burst Write) .......................................... 27 Table 10-10. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 29 Table 10-11. Shift OF SSF and SSV from SADR ................................................................................. 29 Table 10-12. Hit/Miss Assumption ........................................................................................................ 30 Table 10-13. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 35 Table 10-14. Shift OF SSF and SSV from SADR ................................................................................. 35 Table 10-15. Hit/Miss Assumption ........................................................................................................ 36 Table 10-16. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 50 Table 10-17. Shift of SSF and SSV from SADR ................................................................................... 50 Table 10-18. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 52 Table 10-19. Shift OF SSF and SSV from SADR ................................................................................. 52 Table 10-20. Hit/Miss Assumption ........................................................................................................ 53 Table 10-21. Search Latency from Instruction to SRAM Access Cycle ................................................ 58 Table 10-22. Shift OF SSF and SSV from SADR ................................................................................. 58 Table 10-23. Hit/Miss Assumption ........................................................................................................ 59 Table 10-24. The Latency of Search from Instruction to SRAM Access Cycle ..................................... 73 Table 10-25. Shift OF SSF and SSV from SADR ................................................................................. 73 Table 10-26. The Latency of Search from Cycles C and D to SRAM Access Cycle ............................ 76 Table 10-27. Shift OF SSF and SSV from SADR ................................................................................. 76 Table 10-28. Hit/Miss Assumption ........................................................................................................ 76 Table 10-29. The Latency of Search from Cycles C and D to SRAM Access Cycle ............................ 81 Table 10-30. Shift of SSF and SSV from SADR ................................................................................... 81 Table 10-31. Hit/Miss Assumption ........................................................................................................ 82 Table 10-32. The Latency of Search from Cycles C and D to SRAM Access Cycle ............................ 96 Table 10-33. Shift of SSF and SSV from SADR ................................................................................... 96 Table 10-34. Searches with CFG_L Set High ....................................................................................... 98 Table 10-35. Latency of SRAM Write Cycle from Second Cycle of Learn Instruction ........................ 101 Table 12-1. SRAM Address ................................................................................................................ 106 Table 12-2. Required Idle Cycles between Commands ...................................................................... 121 Table 15-1. Supported Operations ..................................................................................................... 124 Table 15-2. TAP Device ID Register ................................................................................................... 125 Table 16-1. DC Electrical Characteristics for CYNSE70128 .............................................................. 125
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CYNSE70128
LIST OF TABLES (continued) Table 16-2. Operating Conditions for CYNSE70128 .......................................................................... 126 Table 17-1. AC Timing Parameters with CLK2X ................................................................................ 126 Table 17-2. AC Timing Parameters with CLK1X ................................................................................ 127 Table 17-3. 2.5V AC Table for Test Condition of CYNSE70128 ........................................................ 127 Table 18-1. Pinout Descriptions for Pinout Diagram ........................................................................... 132 Table 19-1. Ordering Information ........................................................................................................ 135
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CYNSE70128
1.0 Overview
Cypress Semiconductor Corporation's (Cypress's) CYNSE70128 network search engine (NSE) incorporates patent-pending Associative Processing TechnologyTM (APT) and is designed to be a high-performance, pipelined, synchronous, 64K-entry NSE. The CYNSE70128 database entry size can be 72 bits, 144 bits, or 288 bits. In the 72-bit entry mode, the size of the database is 64K entries. In the 144-bit mode, the size of the database is 32K entries, and in the 288-bit mode, the size of the database is 16K entries. The CYNSE70128 device is configurable to support multiple databases with different entry sizes. The 36-bit entry table can be implemented using the Global Mask Registers (GMRs) building-database size of 128K entries with a single device. The NSE can sustain 100 million transactions per second when the database is programmed or configured as 72 or 144 bits. When the database is programmed to have an entry size of 36 or 288 bits, the NSE will perform at 50 million transactions per second. The CYNSE70128 can be used to accelerate network protocols such as Longest-prefix Match (CIDR), ARP, MPLS, and other layer 2, 3, and 4 protocols. This high-speed, high-capacity NSE can be deployed in a variety of networking and communications applications. The performance and features of the CYNSE70128 make it attractive in applications such as Enterprise LAN switches and routers and broadband switching and/or routing equipment supporting multiple data rates at OC-48 and beyond. The NSE is designed to be scalable in order to support network database sizes to 3968K entries specifically for environments that require large network policy databases. The block diagram for the CYNSE70128 device is shown on page 10.
2.0
Features
* 128K 36-bit entries in a single device * 64K entries in 72-bit mode, 32K entries in 144-bit mode, 16K entries in 288-bit mode * 100 million transactions per second in 72- and 144-bit configurations * 50 million transactions in 36- and 288-bit configurations * Searches any subfield in a single cycle * Synchronous pipelined operation * Up to 31 NSEs can be cascaded * When cascaded, the database entries can range up to 3,968K 36-bit entries * Multiple width tables in a single database bank * Glueless interface to industry-standard SRAMs and/or SSRAMs * Simple hardware instruction interface * IEEE 1149.1 test access port * 1.5V core voltage supply up to 83 million searches per second (MSPS)/1.65V core voltage supply for search rates greater than 83 MSPS * 2.5/3.3V I/O voltage supply * 388-pin BGA package.
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CYNSE70128
Block Diagram
CLK_MODE PHS_L CLK1X/CLK2X RST_L Comparand Register Pairs [15:0] Global Mask Register Pairs [15:0] Information and Command Register Burst Read Register Burst Write Register Next-free Address Register Search Successful Index Registers [7:0]
[All registers are 72 bits wide.]
Compare/PIO Data
TAP Controller
TAP
DQ[71:0]
CMD Compare/PIO Data Address Decode Configurable as 64K x 72 32K x 144 16K x 288 Data Array Configurable as 64K x 72 32K x 144 16K x 288 Mask Array Pipeline Priority Encode Match Logic and SRAM Control
SADR[23:0] OE_L WE_L CE_L ALE_L
CMD[10:0] CMDV ACK EOT
Command Decode and PIO Access
ID[4:0] LHI[6:0] FULI[6:0] BHI[2:0] Full Logic FULL FULO[1:0] LHO[1:0] Arbitration Logic BHO[2:0] SSF SSV
3.0
Functional Description
The following subsections contain command and DQ bus (command and databus), database entry, arbitration logic, pipeline and SRAM control, and full logic descriptions.
3.1
Command Bus and DQ Bus
CMD[10:0] carries the command and its associated parameter. DQ[71:0] is used for data transfer to and from the database entries, which comprise a data and a mask field that are organized as data and mask arrays. The DQ bus carries the search data during the Search command as well as the address and data during Read and/or Write operations. The DQ bus also carries the address information for the flow-through accesses to the external SRAMs and/or SSRAMs.
3.2
Database Entry (Data Array and Mask Array)
Each database entry comprises a data and a mask field. The resultant value of the entry is "1," "0," or "X (don't care)," depending on the value in the data and mask bits. The on-chip priority encoder selects the first matching entry in the database that is nearest to location 0.
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CYNSE70128
3.3 Arbitration Logic
When multiple NSEs are cascaded to create large databases, the data being searched is presented to all NSEs simultaneously in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the NSEs will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the SRAM bus.
3.4
Pipeline and SRAM Control
Pipeline latency is added to give enough time to a cascaded system's arbitration logic to determine the device that will drive the index of the matching entry on the SRAM bus. Pipeline logic adds latency to both the SRAM access cycles and the SSF and SSV signals to align them to the host ASIC receiving the associated data.
3.5
Full Logic
Bit[0] in each of the 72-bit entries has a special purpose for the Learn command (0 = empty, 1 = full). When all the data entries have bit[0] = 1, the database asserts the FULL flag, indicating that all the NSEs in the depth-cascaded array are full.
4.0
Signal Descriptions
Table 4-1 lists and describes all CYNSE70128 signals. Table 4-1. CYNSE70128 Signal Description Pin Name CLK_MODE Pin Type[1] I Pin Description
Clock Mode: This signal allows the selection of clock (CLK[2]) input to the CLK1X/CLK2X pin. If the
Clocks and Reset CLK_MODE pin is LOW, CLK2X must be supplied on that pin. PHS_L must also be supplied. If the CLK_MODE pin is HIGH, CLK1X must be supplied on the CLK2X/CLK1X pin, and the PHS_L signal is not required. When the CLK_mode is HIGH, PHS_L is unused and should be externally grounded.
Master Clock: Depending on the CLK_MODE pin, either the CLK2X or the CLK1X must be supplied. CYNSE70128 samples control and data signals on both the edges of CLK1X (if CLK1X is supplied). CYNSE70128 samples all the data and control pins on the positive edge of CLK2X if the CLK2X and PHS_L signals are supplied. All signals are driven out of the device on the rising edge of CLK1X if CLK1X is supplied, and are driven on the rising edge of CLK2X (when PHS_L is low) if CLK2X is supplied. Phase: This signal runs at half the frequency of CLK2X and generates an internal clock from CLK2X.
CLK2X/CLK1X
I
PHS_L RST_L CFG_L
I I I
See "Clocks" on page 13.
Reset: Driving RST_L LOW initializes the device to a known state.
CYNSE70032 and CYNSE70064. When CFG_L is LOW, the CMD[10:9] should be externally grounded. With CFG_L LOW, the device will behave identically with CYNSE70032 and CYNSE70064, and the new feature added to CYNSE70128 will be disabled. When CFG_L is HIGH, the additional command CMD[10:9] can be used and the following additional features will be supported: 1. 16 pair of Global Masks are supported instead of eight; 2. Parallel Write to the data and mask arrays is supported (see "Parallel Write" on page 27); and 3. configuring tables of up to three different widths does not require table identification bits in the data array, thus saving two bits from each 72-bit entry.
Command Bus: [1:0] specifies the command and [10:2] contains the command parameters. The descrip-
Configuration: When CFG_L is LOW, CYNSE70128 will operate in backward compatibility mode with
Command and DQ Bus CMD[10:0] I tions of individual commands explains the details of the parameters. The encoding of commands based on the [1:0] field are: 00: PIO Read 01: PIO Write 10: Search 11: Learn.
Command Valid: This signal qualifies the CMD bus:
CMDV
I
0: No command 1: Command.
Notes: 1. I = Input only, I/O = Input or Output, O = Output only, T = three-state output. 2. "CLK" is an internal clock signal.
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CYNSE70128
Table 4-1. CYNSE70128 Signal Description (continued) Pin Name DQ[71:0] ACK[5] EOT[5] SSF SSV MULTI_HIT HIGH_SPEED Pin Type[1] I/O Pin Description
Address/Data Bus: This signal carries the Read and Write address and data during register, data, and
mask array operations. It carries the compare data during Search operations. It also carries the SRAM address during SRAM PIO accesses.
T
Read Acknowledge: This signal indicates that valid data is available on the DQ bus during register, data, and mask array Read operations, or that the data is available on the SRAM data bus during SRAM Read operations. End of Transfer: This signal indicates the end of burst transfer to the data or mask array during Read or Write burst operations. Search Successful Flag: When asserted, this signal indicates that the device is the global winner in a
T T T O I
Search operation.
Search Successful Flag Valid: When asserted, this signal qualifies the SSF signal. Multiple Hit Flag: When asserted, this signal indicates that there is more than one location having a
match on this device.
High Speed: When this signal is HIGH, the device will run up to 100 MHz and perform 100 MSPS. However, in this mode, a TLSZ value of 00 is not supported when only one device is used. The valid TLSZ values are shown in Command Register Description (Table 7-3). When the signal is LOW, the device will run up to 83 MHz and perform 83 MSPS. SRAM Address: This bus contains address lines to access off-chip SRAMs that contain associative data. See Table 12-1 for the details of the generated SRAM address. In a database of multiple CYNSE70128s, each corresponding bit of SADR from all cascaded devices must be connected. SRAM Chip Enable: This is the chip-enable control for external SRAMs. In a database of multiple
SRAM Interface SADR[23:0] T
CE_L
T
CYNSE70128s, CE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices. CYNSE70128s, WE_L of all cascaded devices must be connected together. This signal is then driven by only one of the devices.
WE_L
T
SRAM Write Enable: This is the write-enable control for external SRAMs. In a database of multiple
OE_L ALE_L
T T
SRAM Output Enable: This is the output-enable control for external SRAMs. Only the last device drives
this signal (with the LRAM bit set).
Address Latch Enable: When this signal is LOW, the addresses are valid on the SRAM address bus. In
a database of multiple CYNSE70128s, the ALE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices.
Cascade Interface LHI[6:0] I
Local Hit In: These pins depth-cascade the device to form a larger table. One signal of this bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block. All unused LHI pins are connected to a logic 0. (For more information, see "Depth-Cascading" on page 102.) Local Hit Out: LHO[1] and LHO[0] are the same logical signal. Either the LHO[1] or the LHO[0] is connected to one input of the LHI bus of up to four downstream devices in a block of up to eight. (For more information see "Depth-Cascading" on page 102.) Block Hit In: Inputs from the previous block BHO[2:0] are tied to BHI[2:0] of the current device. In a four-
LHO[1:0]
O
BHI[2:0]
I
block system, the last block can contain only seven devices because the identification code 11111 is used for broadcast access. devices in the downstream blocks.
BHO[2:0] FULI[6:0]
O I
Block Hit Out: These outputs from the last device in a block are connected to the BHI[2:0] inputs of the Full In: Each signal in this bus is connected to FULO[0] or FULO[1] of an upstream device to generate
the FULL flag for the depth-cascaded block.
Notes: 3. In the previous versions of this specification, this signal was called CLK_OUT. 4. In previous versions of this specification, this signal was called PLL_BYPASS. 5. ACK and EOT require a weak external pull-down such as 47 K or 100 K.
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CYNSE70128
Table 4-1. CYNSE70128 Signal Description (continued) Pin Name FULO[1:0] Pin Type[1] O Pin Description
Full Out: FULO[1] and FULO[0] are the same logical signal. One of these two signals must be connected
to the FULI of up to four downstream devices in a depth-cascaded table. Bit [0] in the data array indicates whether the entry is full (1) or empty (0).This signal is asserted if all bits in the data array are ones. (Refer to "Depth-Cascading" on page 102 for information on how to generate the FULL flag.)
FULL ID[4:0]
O I
Full Flag: When asserted, this signal indicates that the table of multiple depth-cascaded devices is full. Device Identification: The binary-encoded device identification for a depth-cascaded system starts at 00000 and goes up to 11110. 11111 is reserved for a special broadcast address that selects all cascaded NSEs in the system. On a broadcast read-only, the device with the LDEV bit set to 1 responds. Chip core supply: 1.5V. (1.65V for search rates greater than 83 msps.) Chip I/O supply: 2.5V or 3.3V (CYNSE70128-XXX)
Device Identification
Supplies VDD VDDQ Test Access Port TDI TCK TDO TMS TRST_L I I T I I Test access port's test data in. Test access port's test clock. Test access port's test data out. Test access port's test mode select. Test access port's reset. n/a n/a
5.0
Clocks[6]
If the CLK_MODE pin is LOW, CYNSE70128 receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X and generate a CLK, as shown in Figure 5-1. The CYNSE70128 uses CLK2X and CLK for internal operations. Also noted on
"Cycle A End"
CLK2X PHS_L CLK Input Data
"Cycle B End"
A
B
Figure 5-1. CYNSE70128 Clocks (CLK2X and PHS_L) these figures are cycles A and B. Cycle A ends on the rising edge of CLK2X, when PHS_L is high. Cycle B ends on the falling edge of the CLK2X when PHS_L is low. Valid data for cycle A must be available for the NSE at the end of cycle A. Valid data for cycle B must be available for the NSE at the end of cycle B. PHS_L has setup and hold times requirements with respect to CLK2X. The setup and hold time requirements can be referred to in Sections 17.0 AC Timing Waveforms. If the CLK_MODE pin is HIGH, CYNSE70128 receives the CLK1X only. CYNSE70128 uses an internal PLL to double the frequency of CLK1X and then divides that clock by two to generate a CLK for internal operations, as shown in Figure 5-2.[7] CLK1X
CLK Figure 5-2. CYNSE70128 Clocks (CLK1X)
Notes: 6. Any reference to "CLK" cycles means one CLK cycle. 7. For the purpose of showing timing diagrams, all such diagrams in this document will be shown in CLK2X mode. For a timing diagram in CLK1X mode, the following substitution can be made (see Figure 5-3).
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CYNSE70128
CLK2X
PHS_L
Use for CLK2X mode
CLK1X
Use for CLK1X mode Figure 5-3. CYNSE70128 Clocks for All Timing Diagrams
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CYNSE70128
6.0 Phase-Lock Loop Usage
When the device first powers up, it takes 0.5 ms to lock the internal phase-lock loop (PLL). During this locking of the PLL, in addition to 32 extra CLK1X cycles in CLK1X mode and 64 extra cycles in CLK2X mode, the RST_L must be held low for proper initialization of the device. set-up and hold requirements will change in CLK1X mode if the duty cycle of the CLK1X is varied. All signals into the device in CLK1X mode are sampled by a clock that is generated by multiplying CLK1X by two. Since PLL has a locking range, the device will only work between the range of frequencies specified in the timing specification section.
7.0
Registers
All registers in the CYNSE70128 are 72 bits wide. The CYNSE70128 contains 16 pairs of comparand storage registers, 16 pairs of global mask registers (GMRs), eight search successful index registers and one each of command, information, burst Read, burst Write, and next-free address registers. Table 7-1 provides an overview of all the CYNSE70128 registers. The registers are ordered in ascending address order. Each register group is then described in the following subsections. Table 7-1. Register Overview Address 0-31 32-47 96-111 48-55 56 57 58 59 60 61-63 Abbreviation COMP0-31 MASKS SSR0-7 COMMAND INFO RBURREG WBURREG NFA - Type R RW R RW R RW RW R - Name 16 pairs of comparand registers that store comparands from the DQ bus for learning later. 16 global mask register pairs. Eight search successful index registers. Command register. Information register. Burst Read register. Burst Write register. Next-free address register. Reserved.
7.1
Comparand Registers
The device contains 32 72-bit comparand registers (16 pairs) dynamically selected in every Search operation to store the comparand presented on the DQ bus. The Learn command will later use these registers when executed. The CYNSE70128 stores the Search command's cycle A comparand in the even-numbered register and the cycle B comparand in the odd-numbered register, as shown in Figure 7-1. Address 72 72 index 143 0 0 0 1 1 2 3 4 5 6 7
15 30 31 Figure 7-1. Comparand-Register Selection during Search and Learn Instructions
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CYNSE70128
7.2 Mask Registers
The device contains 32 72-bit global mask registers (16 pairs) dynamically selected in every Search operation to select the search subfield. The addressing of these registers is explained in Figure 7-2. The four-bit GMR Index supplied on the command (CMD) bus can apply 16 pairs of global masks during the Search and Write operations, as shown below. Note. In 72-bit Search and Write operations, the host ASIC must program both the even and odd mask registers with the same values. 72 72 0 Index 143 0 0 1 1 2 3 2 4 5 3 6 7 4 8 9 5 10 11 6 12 13 7 14 15 8 16 17 9 18 19 10 20 21 11 22 23 12 24 25 13 26 27 14 28 29 15 30 31 Search and Write command global mask selection Figure 7-2. Addressing the Global Mask Register Array Each mask bit in the GMRs is used during Search and Write operations. In Search operations, setting the mask bit to 1 enables compares; setting the mask bit to 0 disables compares (forced match) at the corresponding bit position. In Write operations to the data or mask array, setting the mask bit to 1 enables Writes; setting the mask bit to 0 disables Writes at the corresponding bit position.
7.3
Search Successful Registers (SSR[0:7])
The device contains eight search successful registers (SSRs) to hold the index of the location where a successful Search occurred. The format of each register is described in Table 7-2. The Search command specifies which SSR stores the index of a specific Search command in cycle B of the Search instruction. Subsequently, the host ASIC can use this register to access that data array, mask array, or external SRAM using the index as part of the indirect access address (see Table 10-4 and Table 7-2). The device with a valid bit set performs a Read or Write operation. All other devices suppress the operation. Table 7-2. Search Successful Register Description Field INDEX Range [15:0] Initial Value X Description Index. This is the address of the 72-bit entry where a successful search occurs. The device updates this field only when the search is successful. If a hit occurs in a 144-bit entry-size quadrant, the LSB is 0. If a hit occurs in a 288-bit entry-size quadrant, the two LSBs are 00. This index updates if the device is either a local or global winner in a Search operation. Reserved. Valid. During Search operation in a depth-cascaded configuration, the device that is a global winner in a match sets this bit to 1. This bit updates only when the device is a global winner in a Search operation. Reserved.
- VALID
[30:16] [31]
0 0
-
[71:32]
0
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CYNSE70128
7.4 Command Register
Table 7-3 describes the command register fields. Table 7-3. Command Register Description Field SRST Range [0] Initial Value 0 Description Software Reset. If 1, this bit resets the device with the same effect as a hardware reset. Internally, it generates a reset pulse lasting for eight CLK cycles. This bit automatically resets to 0 after the reset has completed. Device Enable. If 0, it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L, and ALE_L), SSF, and SSV signals in three-state condition and forces the cascade interface output signals LHO[1:0] and BHO[2:0] to 0. It also keeps the DQ bus in input mode. The purpose of this bit is to make sure that there are no bus contentions when the devices power up in the system. Table Size. The host ASIC must program this field to configure the chips into a table of a certain size. This field affects the pipeline latency of the Search and Learn operations as well as the Read and Write accesses to the SRAM (SADR[23:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the search latency stays constant. Latency in number of CLK cycles with HIGH_SPEED LOW: 00: 1 device 4 01: Up to 8 devices 5 10: Up to 31 devices 6 11: Reserved. Latency number CLK cycles with HIGH_SPEED HIGH: 00: Not supported 01: 1 device 5 10: 2-31 devices 6 11: Reserved. Latency of Hit Signals. This field further adds latency to the SSF and SSV signals during Search, and ACK signal during SRAM Read access by the following number of CLK cycles. 000: 0 100: 4 001: 1 101: 5 010: 2 110: 6 011: 3 111: 7 Last Device in the Cascade. When set, this is the last device in the depthcascaded table and is the default driver for the SSF and SSV signals. In the event of a search failure, the device with this bit set drives the hit signals as follows: SSF = 0, SSV = 1. During nonsearch cycles, the device with this bit set drives the signals as follows: SSF = 0, SSV = 0. Last Device on the SRAM Bus. When set, this device is the last device on the SRAM bus in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L signals. In cycles where no CYNSE70128 device in a depth cascaded table drives these signals, this devices drives the signals as follows: SADR = 24'hFFFFFF, CE_L = 1, WE_L = 1, and ALE_L = 1. OE_L is always driven by the device for which this bit is set.
DEVE
[1]
0
TLSZ
[3:2]
01
HLAT
[6:4]
000
LDEV
[7]
0
LRAM
[8]
0
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CYNSE70128
Table 7-3. Command Register Description (continued) Field CFG Range [24:9] Initial Value 0000000000000000 Description Database Configuration. The device is divided internally into eight partitions of 8K x 72, each of which can be configured as 8K x 72, 4K x 144, or 2K x 288, as follows. 00: 8K x 72 01: 4K x 144 10: 2K x 288 11: low power, partition not used for Search. Bits [10:9] apply to configuring the first partition in the address space. Bits [12:11] apply to configuring the second partition in the address space. Bits [14:13] apply to configuring the third partition in the address space. Bits [16:15] apply to configuring the fourth partition in the address space. Bits [18:17] apply to configuring the fifth partition in the address space. Bits [20:19] apply to configuring the sixth partition in the address space. Bits [22:21] apply to configuring the seventh partition in the address space. Bits [24:23] apply to configuring the eighth partition in the address space. Reserved.
[71:25]
0
7.5
Information Register
Table 7-4 describes the information register fields. Table 7-4. Information Register Description Field Revision Range [3:0] Initial Value 0001 Description Revision Number. This is the current device revision number. Numbers start at one and increment by one for each revision of the device. This is the CYNSE70128 implementation number. Reserved. This is the device identification number. Manufacturer ID. This field is the same as the manufacturer identification number and continuation bits in the TAP controller. Reserved.
Implementation Reserved Device ID MFID
[6:4] [7] [15:8] [31:16]
001 0 00000100 1101_1100_0111_1111
Reserved
[71:32]
7.6
Read Burst Address Register
Table 7-5 shows the Read burst address register (RBURREG) fields which must be programmed before a burst Read. Table 7-5. Read Burst Register Description Field ADR Range [15:0] Initial Value 0 Description Address. This is the starting address of the data or mask array during a burst Read operation. It automatically increments by one for each successive Read of the data or mask array. Once the operation is complete, the contents of this field must be reinitialized for the next operation. Reserved. 0 Length of Burst Access. The device provides the capability to read from 4-511 locations in a single burst. The BLEN decrements automatically. Once the operation is complete, the contents of this field must be reinitialized for the next operation. Reserved.
[18:16] BLEN [27:19]
[71:28]
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CYNSE70128
7.7 Write Burst Address Register Description
Table 7-6 describes the Write burst address register (WBURREG) fields which must be programmed before a burst Write. Table 7-6. Write Burst Register Description Field ADR Range [15:0] Initial Value 0 Description Address. This is the starting address of the data or mask array during a burst Write operation. It automatically increments by one for each successive Write of the data or mask array. Once the operation is complete, the contents of this field must be reinitialized for the next operation. Reserved. 0 Length of Burst Access. The device provides the capability to write from 4-511 locations in a single burst. The BLEN decrements automatically. Once the operation is complete, the contents of this field must be reinitialized for the next operation. Reserved.
[18:16] BLEN [27:19]
[71:28]
7.8
NFA Register
Bit [0] of each 72-bit data entry is specially designated for use in the operation of the Learn command. For 72-bit-configured quadrants, this bit indicates whether a location is full (bit set to 1) or empty (bit set to 0). Every Write and/or Learn command loads the address of the first 72-bit location that contains a 0 in the entry's bit[0]. This is stored in the NFA register (see Table 7-7). If all the bits[0] in a device are set to 1, the CYNSE70128 asserts FULO[1:0] to 1. For a 144-bit-configured quadrants, the LSB of the NFA register is always set to 0. The host ASIC must set both bit[0] and bit[72] in a 144-bit word to either 0 or 1 to indicate full or empty status. Both bit[0] and bit[72] must be set to either 0 or 1, (that is, the 10 or 01 settings are invalid). Table 7-7. NFA Register Address 60 71 - 16 Reserved 15 - 0 Index
8.0
NSE Architecture and Operation Overview
The CYNSE70128 consists of 64K x 72-bit storage cells referred to as data bits. There is a mask cell corresponding to each data cell. Figure 8-1 shows the three organizations of the device based on the value of the CFG bits in the command register. 72 144 288
Masks
16 K 32 K Masks Data
Masks Data CFG = 1010101010101010
64 K
Data
CFG = 0101010101010101 CFG = 0000000000000000 Figure 8-1. CYNSE70128 Database Width Configuration
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CYNSE70128
During a Search operation, the search data bit (S), data array bit (D), mask array bit (M), and global mask bit (G) are used in the following manner to generate a match at that bit position (see Table 8-1). The entry with a match on every bit position results in a successful search during a Search operation. Table 8-1. Bit Position Match G 0 1 1 1 1 1 M X 0 1 1 1 1 D X X 0 1 0 1 S X X 0 0 1 1 Match 1 1 1 0 0 1
In order for a successful search within a device to make the device the local winner in the Search operation, all 72-bit positions must generate a match for a 72-bit entry in 72-bit-configured quadrants, or all 144-bit positions must generate a match for two consecutive even and odd 72-bit entries in quadrants configured as 144 bits, or all 288-bit positions must generate a match for four consecutive entries aligned to four entry-page boundaries of 72-bit entries in quadrants configured as 288 bits. An arbitration mechanism using a cascade bus determines the global winning device among the local winning devices in a Search cycle. The global winning device drives the SRAM bus, SSV, and the SSF signals. In case of a Search failure, the device(s) with the LDEV and LRAM bits set drive(s) the SRAM bus, SSF, and SSV signals. The CYNSE70128 device can be configured to contain tables of different widths, even within the same chip. Figure 8-2 shows a sample configuration of different widths.
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CYNSE70128
72 8K 72 8K 72 8K 72 8K 144 144 288 288
4K 4K 2K 2K
CFG = 10 10 01 01 11 11 00 00 Inactive (low power) Figure 8-2. Multiwidth Database Configurations Example
9.0
Data and Mask Addressing
72 71 0 1 2 3 64K 0 72 283 16K 0 4 65532 1 5 65533 2 6 65534 3 7 32K 65535 72 72 72 0 72 143 0 2 4 6 1 3 5 7 72 0
Figure 9-1 shows CYNSE70128 data and mask array addressing.
CFG = 1010101010101010 65534 65535 65535 (288-bit configuration) CFG = 0101010101010101 CFG = 0000000000000000 (144-bit configuration) (72-bit configuration) Figure 9-1. Addressing the CYNSE70128 Data and Mask Arrays
10.0
Commands
A master device such as an ASIC controller issues commands to the CYNSE70128 device using the command valid (CMDV) signal and the CMD bus. The following subsections describe the operation of the commands.
10.1
Command Codes
The CYNSE70128 implements four basic commands, shown in Table 10-1. The command code must be presented to CMD[1:0] while keeping the CMDV signal high for two CLK2X cycles (designated as cycles A and B) when the CLK_MODE pin is low. In CLK2X mode, the controller ASIC must align the instructions using the PHS_L signal. The command code must be presented to CMD[1:0] while keeping the CMDV signal high for one CLK1X cycle when the CLK_MODE pin is high. In CLK1X mode the high phase of the CLK1X is designated as cycle A and the low phase of the CLK1X is designated as cycle B. The CMD[10:2] field passes the parameters of the command in cycles A and B. Document #: 38-02040 Rev. *F Page 21 of 137
CYNSE70128
Table 10-1. Command Codes Command Code 00 01 10 11 Command Read Write Search Learn[8] Description Reads one of the following: data array, mask array, device registers, or external SRAM. Writes one of the following: data array, mask array, device registers, or external SRAM. Searches the data array for a desired pattern using the specified register from the GMR array and local mask associated with each data cell. The device has internal storage for up to 16 comparands that it can learn. The device controller can insert these entries at the next free address (as specified by the NFA register) using the Learn instruction.
10.2
Commands and Command Parameters
Table 10-2 lists the CMD bus fields that contain the CYNSE70128 command parameters and their respective cycles. Each command is described separately in the subsections that follow. Table 10-2. Command Parameters CMD[9, 10] CYC Read A B Write A 10 X X Global Mask Register Index[9] Global Mask Register Index[9] Global Mask Register Index[10] X X X X X 9 X X 8 7 6 5 0 0 4 0 0 3 0 0 2 0 = Single 1 = Burst 0 = Single 1 = Burst 0 = Single 1 = Burst 1 0 0 0 0 0 0 1
SADR[23] SADR[22] SADR[21] 0 0 0
0 Normal SADR[23] SADR[22] SADR[21] Write 1 Parallel Write 0 Normal Write 1 Parallel Write 0 0 0
Global Mask Register Index [2:0] Global Mask Register Index [2:0] Global Mask Register Index [2:0]
B
0 = Single 1 = Burst
0
1
Search
A
72 bit: 0 SADR[23] SADR[22] SADR[21] 144-bit: 1 288 bit: X Successful Search Register Index[2:0] SADR[23] SADR[22] SADR[21] 0 0 Mode 0: 72-bit 1: 144-bit
72-bit or 144-bit: 0 288-bit: 1 in 1st cycle 0 in 2nd cycle
1
0
B Learn[8] A B
Comparand Register Index Comparand Register Index Comparand Register Index
1 1 1
0 1 1
10.3
Read Command
The Read can be a single Read of a data array, a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst Read of the data (CMD[2] = 1) or mask array locations using an internal auto-incrementing address register (RBURADR). A description of each type is provided in Table 10-3. A single-location Read operation lasts six cycles, as shown in Figure 10-1. The burst Read adds two cycles for each successive Read. The SADR[23:21] bits supplied in the Read instruction cycle A drives SADR[23:21] signals during the Read of an SRAM location.
Notes: 8. The 288-bit-configured devices or 288-bit-configured quadrants within devices do not support the Learn instruction. Also, CLK1X must be less than 8 3MHz. 9. Use only CMD[8:0] and connect the CMD[10:9] to ground with CFG_L LOW. 10. For a description of CMD[9] and CMD[2], see subsections on search 288-bit configured tables and mixed-size searches with CFG_L HIGH.
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CYNSE70128
cycle 1 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ ACK Figure 10-1. Single-Location Read Cycle Timing Table 10-3. Read Command Parameters CMD Parameter CMD[2] Read Command 0 1 Single Read Burst Read Description Reads a single location of the data array, mask array, external SRAM, or device registers. All access information is applied on the DQ bus. Reads a block of locations from the data array, or mask array as a burst. The internal register (RBURADR) specifies the starting address and the length of the data transfer from the data or mask array, and it auto-increments the address for each access. All other access information is applied on the DQ bus. Note. The device registers and external SRAM can only be read in single-Read mode. Read A B FF Data cycle 2 cycle 3 cycle 4 cycle 5 cycle 6
Address
The single Read operation takes six clock cycles, in the following sequence. * Cycle 1: The host ASIC applies the Read instruction on the CMD[1:0] (CMD[2]= 0) using CMDV = 1 and the DQ bus supplies the address, as shown in Table 10-4 and Table 10-5. The host ASIC selects the CYNSE70128 for which ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70128 with the LDEV bit set. The host ASIC also supplies SADR[23:21] on CMD[8:6] in cycle A of the Read instruction if the Read is directed to the external SRAM. * Cycle 2: The host ASIC floats DQ[71:0] to three-state condition. * Cycle 3: The host ASIC keeps DQ[71:0] in three-state condition. * Cycle 4: The selected device starts to drive the DQ[71:0] bus, and drives the ACK signal from Z to LOW. * Cycle 5: The selected device drives the read data from the addressed location on the DQ[71:0] bus, and drives the ACK signal HIGH. * Cycle 6: The selected device floats the DQ[71:0] to three-state condition and drives the ACK signal LOW. At the termination of cycle 6, the selected device releases the ACK line to three-state condition. The Read instruction is complete, and a new operation can begin. Note. The latency of the SRAM Read will be different than the one described above (see "SRAM PIO Access" on page 106). Table 10-4 lists and describes the format of the Read address for a data array, mask array, or SRAM. Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM DQ[71:30] Reserved DQ[29] DQ[28:26] DQ[25:21] DQ[20:19] DQ[18:16] DQ[15:0] 0: Direct Successful ID 00: Data Reserved If DQ[29] is 0, this field carries the address of 1: Indirect Search Register Array the data array location. If DQ[29] is 1, the SSRI Index (applispecified on DQ[28:26] is used to generate the address of the data array location: {SSR[15:2], cable if DQ[29] SSR[1] | DQ[1], SSR[0] | DQ[0]}.[11] is indirect)
Note: 11. "|" stands for logical OR operation. "{}" stands for concatenation operator.
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CYNSE70128
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM (continued) DQ[71:30] Reserved DQ[29] DQ[28:26] DQ[25:21] DQ[20:19] DQ[18:16] DQ[15:0] 0: Direct Successful ID 01: Mask Reserved If DQ[29] is 0, this field carries the address of 1: Indirect Search Register Array the mask array location. If DQ[29] is 1, the Index (appliSSRI specified on DQ[28:26] is used to generate the address of the mask array cable if DQ[29] location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | is indirect) DQ[0]}.[11] 0: Direct Successful ID 10: Reserved If DQ[29] is 0, this field carries the address of 1: Indirect Search Register External the SRAM location. If DQ[29] is 1, the SSRI Index (appliSRAM specified on DQ[28:26] is used to generate the address of the SRAM location: {SSR[15:2], cable if DQ[29] SSR[1] | DQ[1], SSR[0] | DQ[0]}.[11] is indirect)
Reserved
Table 10-5 describes the Read address format for the internal registers. Figure 10-2 illustrates the timing diagram for the burst Read of the data or mask array. Table 10-5. Read Address Format for Internal Registers DQ[71:26] Reserved DQ[25:21] ID DQ[20:19] 11: Register DQ[18:7] Reserved DQ[6:0] Register Address
cycle cyclecycle cyclecyclecycle cycle cyclecyclecycle cyclecycle 1 2 3 4 5 6 7 8 9 10 11 12 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ ACK EOT Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4) The Read operation lasts 4 + 2n CLK cycles (where n is the number of accesses in the burst specified by the BLEN field of the RBURREG) in the sequence shown below. This operation assumes that the host ASIC has programmed the RBURREG with the starting address (ADR) and the length of the transfer (BLEN) before initiating the burst Read command. * Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address supplied on the DQ bus, as shown in Table 10-6. The host ASIC selects the CYNSE70128 where ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70128 with the LDEV bit set. * Cycle 2: The host ASIC floats DQ[71:0] to the three-state condition. * Cycle 3: The host ASIC keeps DQ[71:0] in the three-state condition. * Cycle 4: The selected device starts to drive the DQ[71:0] bus and drives ACK and EOT from Z to LOW. * Cycle 5: The selected device drives the Read data from the addressed location on the DQ[71:0] bus, and drives the ACK signal HIGH. Cycles 4 and 5 repeat for each additional access until all the accesses specified in the burst length (BLEN) field of RBURREG are complete. On the last transfer, the CYNSE70128 drives the EOT signal high. * Cycle (4 + 2n): The selected device drives the DQ[71:0] to the three-state condition, and drives the ACK and EOT signals LOW. At the termination of cycle (4 + 2n), the selected device floats the ACK line to the three-state condition. The burst Read instruction is complete, and a new operation can begin. Table 10-6 describes the Read address format for data and mask arrays for burst Read operations. Document #: 38-02040 Rev. *F Page 24 of 137 Read AB Address FF Data0 FF Data1 FF Data2 FF Data3
CYNSE70128
Table 10-6. Read Address Format for Data and Mask Arrays DQ[71:26] Reserved DQ[25:21] ID DQ[20:19] 00: Data Array DQ[18:16] Reserved DQ[15:0]
Do not care. These 16 bits come from the internal register (RBURADR) which increments for each access. Do not care. These 16 bits come from the internal register (RBURADR) which increments for each access.
Reserved
ID
01: Mask Array
Reserved
10.4
Write Command
The Write can be a single Write of a data array, mask array, register, or external SRAM location (CMD[2] = 0). It can be a burst Write (CMD[2] = 1) using an internal auto-incrementing address register (WBURADR) of the data or mask array locations. A single-location Write is a three-cycle operation, as shown in Figure 10-3. The burst Write adds one extra cycle for each successive location Write. cycle 0 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ A Write B Address Data X cycle 1 cycle 2 cycle 3 cycle 4
Figure 10-3. Single Write Cycle Timing The following is the Write operation sequence, and Table shows the Write address format for the data array, the mask array, or the single-Write SRAM. Table 10-8 shows the Write address format for the internal registers. * Cycle 1A: The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the address supplied on the DQ bus. The host ASIC also supplies the GMR Index to mask the Write to the data or mask array location on {CMD[10],CMD[5:3]}. For SRAM Writes, the host ASIC must supply the SADR[23:21] on CMD[8:6]. The host ASIC sets CMD[9] to 0 for the normal Write. * Cycle 1B:The host ASIC continues to apply the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask array locations in {CMD[10], CMD[5:3]}.The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects all the devices when DQ[25:21] = 11111. * Cycle 2: The host ASIC drives the DQ[71:0] with the data to be written to the data array, mask array, or register location of the selected device. * Cycle 3: Idle cycle. At the termination of cycle 3, another operation can begin. Note. The latency of the SRAM Write will be different than the one described above (see "SRAM PIO Access" on page 106).
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Table 10-7. Write Address Format for Data Array, Mask Array or SRAM (Single Write) DQ[71:30] Reserved DQ[29] DQ[28:26] DQ[25:21] DQ[20:19] DQ[18:16] DQ[15:0] 0: Direct SSR (appliID 00: Data Array Reserved If DQ[29] is 0, this field carries the address of 1: Indirect cable if DQ[29] the data array location. is indirect) If DQ[29] is 1, the SSR specified on DQ[28:26] is used to generate the address of data array location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | DQ[0]} [Figure 10-4].[12] Reserved 0: Direct SSR (appliID 01: Mask Array Reserved If DQ[29] is 0, this field carries the address of 1: Indirect cable if DQ[29] the mask array location. If DQ[29] is 1, the SSR specified on DQ[28:26] is indirect) is used to generate the address of the mask array location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | DQ[0]} [Figure 10-4]. Reserved 0: Direct SSR (appliID 10: External Reserved If DQ[29] is 0, this field carries the address of 1: Indirect cable if DQ[29] SRAM the SRAM location. If DQ[29] is 1, the SSR specified on DQ[28:26] is indirect) is used to generate the address of SRAM location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | DQ[0]} [Figure 10-4].
a
Table 10-8. Write Address Format for Internal Registers DQ[71:26] Reserved DQ[25:21] ID DQ[20:19] 11: Register DQ[18:7] Reserved DQ[6:0] Register address
Figure 10-4 shows the timing diagram of a burst Write operation of the data or mask array. cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ EOT Figure 10-4. Burst Write of the Data and Mask Arrays (BLEN = 4) The burst Write operation lasts for (n + 2) CLK cycles. n signifies the number of accesses in the burst as specified in the BLEN field of the WBURREG register. The following is the block Write operation sequence. This operation assumes that the host ASIC has programmed the WBURREG with the starting address (ADR) and the length of transfer (BLEN) before initiating a burst Write command. * Cycle 1A: The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the address supplied on the DQ bus, as shown in Table 10-9. The host ASIC also supplies the GMR Index to mask the Write to the data or mask array locations in {CMD[10], CMD[5:3]}. The host ASIC sets CMD[9] to 0 for the normal Write. * Cycle 1B: The host ASIC continues to apply the Write instruction on the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask array locations in {CMD[10], CMD[5:3]}. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. It selects all the devices when DQ[25:21] = 11111. * Cycle 2: The host ASIC drives the DQ[71:0] with the data to be written to the data or mask array location of the selected device. The CYNSE70128 writes the data from the DQ[71:0] bus only to the subfield that has the corresponding mask bit set to 1 in the GMR specified by the index {CMD[10],CMD[5:3]} supplied in cycle 1.
Note: 12. "|" stands for logical OR operation. "{}" stands for concatenation operator.
Write A B X
Address Data0 Data1 Data2 Data3
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* Cycles 3 to n + 1: The host ASIC drives the DQ[71:0] with the data to be written to the next data or mask array location (addressed by the auto-increment ADR field of the WBURREG register) of the selected device. The CYNSE70128 writes the data on the DQ[71:0] bus only to the subfield that has the corresponding mask bit set to 1 in the GMR specified by the index {CMD[10],CMD[5:3]} supplied in cycle 1. The CYNSE70128 drives the EOT signal low from cycle 3 to cycle n; the CYNSE70128 drives the EOT signal high in cycle n + 1 (n is specified in the BLEN field of the WBURREG). * Cycle n + 2: TheCYNSE70128 drives the EOT signal LOW. At the termination of cycle n + 2, the CYNSE70128 floats the EOT signal to a three-state operation, and a new instruction can begin. Table 10-9. Write Address Format for Data and Mask Array (Burst Write) DQ[71:26] Reserved Reserved DQ[25:21] ID ID DQ[20:19] 00: Data array 01: Mask array DQ[18:16] Reserved Reserved DQ[15:0]
Do not care. These 16 bits come from the internal register (WBURADR), which increments with each access. Do not care. These 16 bits come from the internal register (WBURADR), which increments with each access.
10.5
Parallel Write
In order to write the data and mask arrays faster for initialization, testing, or diagnostics, many locations can be written simultaneously in the CYNSE70128 device using Parallel Write. Parallel Write allows the user to specify one address and write multiple locations in the data or mask array with the same data.In order to perform Parallel Write, CMD[9] should be set in cycles A and B of the Write command to the data or mask arrays. The address bits DQ[10:1] specify which location to perform parallel write to. DQ[15:11] defines a set of 32 partitions all of which write two 72 bit entries (DQ[0] is ignored). Thus 64 72-bit locations are simultaneously written in either the data or mask array during Parallel Write.
10.6
Search Command
This subsection describes the following: * 72-bit search on tables configured as x72 using one device * 72-bit search on tables configured as x72 using up to eight devices * 72-bit search on tables configured as x72 using up to 31 devices * 144-bit search on tables configured as x144 using one device * 144-bit search on tables configured as x144 using up to eight devices * 144-bit search on tables configured as x144 using up to 31 devices * 288-bit search on tables configured as x288 using one device * 288-bit search on tables configured as x288 using up to eight devices * 288-bit search on tables configured as x288 using up to 31 devices * Mixed-size searches on tables configured with different widths using an CYNSE70128 with CFG_L low * Mixed-size searches on tables configured with different widths using an CYNSE70128 with CFG_L high. 10.6.1 72-bit Search on Tables Configured as x72 Using a Single CYNSE70128 Device
Figure 10-5 shows the timing diagram for a Search command in the 72-bit-configured table (CFG = 0000000000000000) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1. The hardware diagram for this search subsystem is shown in Figure 10-6.
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 2 3 4 5 6 7 8 9 10 1 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 1 1 1 0 0 0 Search1 Hit 1 01 Search3 01 01 01 Search2 Search4
A B AB A BAB D1 D2 D3 D4
A1 0 0 1 0 1 1 1 0 1 0
A3 0 0 1 0 1 1 1 0 0 1 0 Search4 Miss
Search3 Hit Search2 Miss CFG = 0000000000000000, HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1.
Figure 10-5. Timing Diagram for 72-bit Search in x72 Table (One Device) BHI[2:0] 6
CYNSE70128
DQ[71:0] CMDV, CMD10:0] SSF, SSV
5
4
3 LHI
2
1
0 SRAM LHO[0]
BHI[2:0]
LHO[1]
Figure 10-6. Hardware Diagram for a Table with One Device The following is the sequence of operation for a single 72-bit search command (also refer to "Command and Command Parameters," Subsection 10.2 on page 22). * Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72-bit data to be compared. The CMD[2] signal must be driven to logic 0. * Cycle B: The host ASIC continues to drive the CMDV high and to apply Search command (10) on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles A Document #: 38-02040 Rev. *F Page 28 of 137
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and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag (see page 8 for information on SSR[0:7]). The DQ[71:0] continues to carry the 72-bit data to be compared.
Note. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B. The even
and odd pair of GMRs selected for the compare must be programmed with the same value.
The logical 72-bit Search operation is shown in Figure 10-7. The entire table consisting of 72-bit entries is compared to a 72-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs selected by the GMR Index in the command's cycle A. The 72-bit word K (presented on the DQ bus in both cycles A and B of the command) is also stored in both even and odd comparand register pairs selected by the Comparand Register Index in the command's cycle B. In a x72 configuration, only the even comparand register can be subsequently used by the Learn command. The word K (presented on the DQ bus in both cycles A and B of the command) is compared with each entry in the table starting at location 0. The first matching entry's location address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see "SRAM Addressing" on page 105). 0 71 GMR K Location address 0 71 0 1 Comparand Register (even) 2 K 3 Comparand Register (odd) K L 65535 CFG = 0000000000000000 (288-bit configuration) Figure 10-7. x72 Table with One Device The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 72-bit searches in x72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command cycle (two CLK2X cycles) is shown in Table 10-10. Table 10-10. The Latency of Search from Instruction to SRAM Access Cycle Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 64K x 72 bits 512K x 72 bits 1984K x 72 bits Latency in CLK Cycles 4 5 6 71 0
(First matching entry)
The latency of a Search from command to SRAM access cycle is 4 for a single device in the table and TLSZ = 00. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-11. Table 10-11. Shift OF SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7
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10.6.2 72-bit Search on Tables Configured as x72 Using up to Eight CYNSE70128 Devices The hardware diagram of the search subsystem of eight devices is shown in Figure 10-8. The following are the parameters programmed into the eight devices. * First seven devices (device 0-6): CFG = 0000000000000000, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0. * Eighth device (device 7): CFG = 0000000000000000, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1. Note. All eight devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table (device number 7 in this case) must be programmed with LRAM = 1 and LDEV = 1. All other upstream devices (devices 0 through 6 in this case) must be programmed with LRAM = 0 and LDEV = 0. Figure 10-9 shows the timing diagram for a Search command in the 72-bit-configured table of eight devices for device number 0. Figure 10-10 shows the timing diagram for a Search command in the 72-bit-configured table of eight devices for device number 1. Figure 10-11 shows the timing diagram for a Search command in the 72-bit-configured table of eight devices for device number 7 (the last device in this specific table). For these timing diagrams four 72-bit searches are performed sequentially. Hit/Miss assumptions were made as shown below in Table 10-12. Table 10-12. Hit/Miss Assumption Search Number Device 0 Device 1 Device 2-6 Device 7 1 Hit Miss Miss Miss 2 Miss Hit Miss Miss 3 Hit Hit Miss Hit 4 Miss Miss Miss Hit
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SRAM BHI[2:0] LHO[1] SSF, SSV 6 5 4
CYNSE70128 #0
3 LHI
2
1
0 LHO[0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #1
3 LHI
2
1 LHO[0]
0
DQ[71:0] CMDV CMD[10:0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #2
3 LHI
2 LHO[0]
1
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #3
3 2 LHI LHO[0]
1
0
BHI[2:0]
6
5
CYNSE70128 #4
3 LHI LHO[0]
4
2
1
0
BHI[2:0] 3
21 LHI
0
LHI CYNSE70128 #5 LHO[0]
6
5
4
BHI[2:0] 3
2 1 LHI
0
6 LHO[0]
CYNSE70128 #6
5 4 LHI
BHI[2:0]3
2
1 LHI
0
6
CYNSE70128 #7
5 LHI
4 BHO[0] BHO[1] BHO[2]
BHO[0] BHO[1] BHO[2]
LHO[1] LHO[0] Figure 10-8. Hardware Diagram for a Table with Eight Devices
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF z z z z z z z 1 1 Search1 (This device is the global winner.) Search2 (Miss on this device.) CFG = 0000000000000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0. Note: |(LHI[6:0]) stands for the boolean `OR' of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal. Search3 (This device is the global winner.) z z 1 1 z z A1 0 0 1 z z z z A3 0 0 1 z z z z 0 01 Search3 01 01 01 Search2 Search4
A B AB A BAB D1 D2 D3 D4
Search4 (Miss on this device.) Figure 10-9. Timing Diagram for 72-bit Search Device Number 0
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF z z z z z z z 1 1 z z A2 0 0 1 z z z 01 Search3 01 01 01 Search2 Search4
A B AB A BAB D1 D2 D3 D4
Search3 (Local winner but not global winner.) CFG = 0000000000000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0. Search2 Search4 Note: |(LHI[6:0]) stands for the boolean `OR' of the entire bus LHI[6:0]. (Miss (This Note: Each bit in LHO[1:0] is the same logical signal. device is on this device.) global winner.) Figure 10-10. Timing Diagram for 72-bit Search Device Number 1
Search1 (Miss on this device.)
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 1 0 0 0 z z 1 1 0 0 z z z A4 0 0 1 01 Search3 01 01 01 Search2 Search4
A B AB A BAB D1 D2 D3 D4
z
CFG = 0000000000000000, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1. Note: |(LHI[6:0]) stands for the boolean `OR' of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3 (Local but not (Miss on this global winner) .) deviceSearch2 Search4 (Miss on (Global this device) winner) Figure 10-11. Timing Diagram for 72-bit Search Device Number 7 (Last Device)
The following is the sequence of operation for a single 72-bit Search command (also refer to "Command and Command Parameters," Subsection 10.2 on page 22). * Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) to CMD[1:0] signals. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72bit data to be compared. The CMD[2] signal must be driven to logic 0. * Cycle B: The host ASIC continues to drive the CMDV high and to apply Search command (10) on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and hit flag (see page 8 for a description of SSR[0:7]). The DQ[71:0] continues to carry the 72-bit data to be compared.
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Note. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B, and the even
and odd pairs of GMRs selected for the comparison must be programmed with the same value.
The logical 72-bit Search operation is shown in Figure 10-12. The entire table with eight devices of 72-bit entries is compared to a 72-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and selected by the GMR Index in the command's cycle A. The 72-bit word K (presented on the DQ bus in both cycles A and B of the command) is also stored in both even and odd comparand register pairs (selected by the Comparand Register Index in command cycle B) in each of the eight devices. In the x72 configuration, only the even comparand register can subsequently be used by the Learn command in one of the devices (only the first non-full device). The word K (presented on the DQ bus in both cycles A and B of the command) is compared with each entry in the table starting at location 0. The first matching entry's location address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see "SRAM Addressing" on page 105). The global winning device will drive the bus in a specific cycle. On a global miss cycle the device with LRAM = 1 (default driving device for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV signals) will be the default driver for such missed cycles. 71 Must be same in each of the eight devices Location 71 address 0 71 0 1 Comparand Register (Even) 2 K 3 Comparand Register (Odd) K L GMR K 0 0
(First matching entry) Will be same in each of the eight devices 524287 CFG = 0000000000000000 (72-bit configuration)
Figure 10-12. x72 Table with Eight Devices The Search command is a pipelined operation and executes a search at half the rate of the frequency of CLK2X for 72-bit searches in x72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command cycle (two CLK2X cycles) is shown in Table 10-13. Table 10-13. The Latency of Search from Instruction to SRAM Access Cycle Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 64K x 72 bits 512K x 72 bits 1984K x 72 bits Latency in CLK Cycles 4 5 6
The latency of the search from command to SRAM access cycle is 5 for up to eight devices in the table (TLSZ = 01). SSV and SSF also shift further to the right for different values of HLAT, as specified in Table 10-14. Table 10-14. Shift OF SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Document #: 38-02040 Rev. *F Number of CLK Cycles 0 1 2 3 4 5 6 7 Page 35 of 137
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10.6.3 72-bit Search on Tables Configured as x72 Using up to 31 CYNSE70128 Devices The hardware diagram of the search subsystem of 31 devices is shown in Figure 10-13. Each of the four blocks in the diagram represents eight CYNSE70128 devices (except the last, which has seven devices). The diagram for a block of eight devices is shown in Figure 10-14. The following are the parameters programmed into the 31 devices. * First thirty devices (devices 0-29): CFG = 0000000000000000, TLSZ = 10, HLAT = 001, LRAM = 0, and LDEV = 0. * Thirty-first device (device 30): CFG = 0000000000000000, TLSZ = 10, HLAT = 001, LRAM = 1, and LDEV = 1. Note. All 31 devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table must be programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case). The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 10-15. For the purpose of illustrating the timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. Figure 1015 shows the timing diagram for a Search command in the 72-bit-configured table of 31 devices for each of the eight devices in block 0. Figure 10-16 shows a timing diagram for a Search command in the 72-bit-configured table of 31 devices for the all the devices in block number 1 (above the winning device in that block). Figure 10-17 shows the timing diagram for the globally winning device (defined as the final winner within its own and all blocks) in block number 1. Figure 10-18 shows the timing diagram for all the devices below the globally winning device in block number 1. Figure 10-19, Figure 10-20, and Figure 10-21 show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winning device, respectively, for block number 2. Figure 10-22, Figure 10-23,Figure 10-24, and Figure 10-25 show the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the globally winning device except the last device (device 30), respectively, for block number 3. The 72-bit Search operation is pipelined and executes as follows. Four cycles from the Search command, each of the devices knows the outcome internal to it for that operation. In the fifth cycle after the Search command, the devices in a block arbitrate for a winner amongst them (a "block" being defined as less than or equal to eight devices resolving the winner within them using the LHI[6:0] and LHO[1:0] signalling mechanism). In the sixth cycle after the Search command, the blocks (of devices) resolve the winning block through the BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device for a Search operation. Table 10-15. Hit/Miss Assumption Search Number Block 0 Block 1 Block 2 Block 3 1 Miss Miss Miss Hit 2 Miss Miss Hit Hit 3 Miss Hit Hit Miss 4 Miss Miss Miss Miss
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BHI[2] SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70128s Block 0 (Devices 0-7) BHO[1] BHO[0] BHO[2]
SRAM
BHI[2] BHI[1] BHI[0] GND Block of 8 CYNSE70128s Block 1 (Devices 8-15) BHO[2] BHO[1] BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70128s Block 2 (Devices 16-23) BHO[2] BHO[1] BHO[0]
BHI[1] BHI[0] BHI[2] Block of 7 CYNSE70128s Block 3 (Devices 24-30) DQ[71:0] CMD[10:0], CMDV BHO[2] BHO[1] BHO[0] Figure 10-13. Hardware Diagram for a Table with 31 Devices
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BHI[2:0] SRAM BHI[2:0] LHO[1] 6 5 4
CYNSE70128 #0
3 LHI
2
1
0 LHO[0]
BHI[2:0] DQ[71:0] CMDV CMD[10:0] SSV, SSF LHO[1]
6
5
4
CYNSE70128 #1
3 LHI
2
1 LHO[0]
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #2
3 LHI
2 LHO[0]
1
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #3
3 2 LHI LHO[0]
1
0
BHI[2:0]
6
5
CYNSE70128 #4
3 LHI LHO[0]
4
2
1
0
BHI[2:0] 3
21 LHI
0
LHI CYNSE70128 #5 LHO[0]
6
5
4
BHI[2:0] 3
2 1 LHI
0
6 LHO[0]
CYNSE70128 #6
5 4 LHI
BHI[2:0]3
2
1 LHI
0
6
CYNSE70128 #7
5 LHI
4 BHO[0] BHO[1] BHO[2] LHO[1] LHO[0]
BHO[0] BHO[1] BHO[2]
Figure 10-14. Hardware Diagram for a Block of up to Eight Devices
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Figure 10-15. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device)
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0)] stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-16. Timing Diagram for Each Device Above the Winning Device in Block Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) z z Search3 (This device global winner.) Search2 Search4 (Miss (Miss on this on this device.) device.) A3 z z z z 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-17. Timing Diagram for Globally Winning Device in Block Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-18. Timing Diagram for Devices Below the Winning Device in Block Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-19. Timing Diagram for Devices Above the Winning Device in Block Number 2
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z 0 z z z z z Search1 (Miss on this device.) 1 1 z z 0 1 A2 z z z z 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (Hit but not winner.) Search2 Search4 (Miss (Global winner.) on this device.)
Figure 10-20. Timing Diagram for Globally Winning Device in Block Number 2
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 Search4 (Miss on (Miss on this this device.) device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-21. Timing Diagram for Devices Below the Winning Device in Block Number 2
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Figure 10-22. Timing Diagram for Devices Above the Winning Device in Block Number 3
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z 0 z 0 z z z z 1 1 Search1 (Global winner. ) z z Search3 (Miss on this device.) Search2 Search4 (Miss (Hit on this but not device.) global winner.) 1 A1 z z z z 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-23. Timing Diagram for Globally Winning Device in Block Number 3
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (Miss on this device.) Search2 Search4 (Miss on (Miss on this this device.) device.) Figure 10-24. Timing Diagram for Devices Below the Winning Device in Block Number 3 (Except the Last Device [Device 30])
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 1 0 0 0 0 0 0 0 z z z 0 0 1 z z 1 0 01 Search3 01 01 01 Search2 Search4 A B AB A BAB D1 D2 D3 D4
z
CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1. Note: |(BHI[2:0)] stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3 (Hit on (Hit on some some device device above.) above.) Search2 Search4 (Global (Hit on miss; this device some default device above.) driver.)
Figure 10-25. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) The following is the sequence of operation for a single 72-bit Search command (also refer to the "Command and Command Parameters," on page 22). * Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72bit data to be compared. The CMD[2] signal must be driven to a logic 0. * Cycle B: The host ASIC continues to drive the CMDV high and applies Search command (10) on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag (see page 16 for the description of SSR[0:7]). The DQ[71:0] continues to carry the 72-bit data to be compared.
Note. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B and the even
and odd pair of GMRs selected for the compare must be programmed with the same value.
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The logical 72-bit Search operation is shown in Figure 10-26. The entire table (31 devices of 72-bit entries) is compared to a 72bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and selected by the GMR Index in the command's cycle A. The 72-bit word K (presented on the DQ bus in both cycles A and B of the command) is also stored in both even and odd comparand register pairs in each of the eight devices and selected by the Comparand Register Index in command's cycle B. In the x72 configuration, the even comparand register can be subsequently used by the Learn command only in the first non-full device. The word K (presented on the DQ bus in both cycles A and B of the command) is compared with each entry in the table starting at location 0. The first matching entry's location address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see "SRAM Addressing" on page 105). The global winning device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 and LDEV = 1 will be the default driver for such missed cycles. 71 Must be same in each of the 31 devices Location 71 address 0 71 0 1 Comparand Register (even) 2 K 3 Comparand Register (odd) K L 2031615 Will be same in each of the 31 devices CFG = 0000000000000000 (72-bit configuration) GMR K 0 0
(First matching entry)
Figure 10-26. x72 Table with 31 Devices The Search command is a pipelined operation and executes a search at half the rate of the frequency of CLK2X for 72-bit searches in x72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit Search command cycle (two CLK2X cycles) is shown in Table 10-16. Table 10-16. The Latency of Search from Instruction to SRAM Access Cycle Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 64K x 72 bits 512K x 72 bits 1984K x 72 bits Latency in CLK Cycles 4 5 6
For up to 31 devices in the table (TLSZ = 10), search latency from command to SRAM access cycle is 6. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-17. Table 10-17. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7
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10.6.4 144-bit Search on Tables Configured as x144 Using a Single CYNSE70128 Device Figure 10-27 shows the timing diagram for a Search command in the 144-bit-configured table (CFG = 0101010101010101) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this search subsystem is shown in Figure 10-28. cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] 01 Search3 01 01 01 Search2 Search4
A B AB A BAB A B AB A BAB D1 D2 D3 D4 A1 1 1 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 1 0 A3 0 0 1 0 1 1 1 0 0
DQ SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF
Search1 Search3 CFG = 0101010101010101, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1. Search2 Search4 Hit Miss Hit Miss Figure 10-27. Timing Diagram for 144-bit Search (One Device)
DQ[71:0] CMDV, CMD[10:0] SSF, SSV
BHI[2:0]
6
CYNSE70128
5
4
3 LHI
2
1
0 SRAM LHO[0]
BHO[2:0]
LHO[1]
Figure 10-28. Hardware Diagram for a Table With One Device The following is the operation sequence for a single 144-bit Search command (also refer to "Command and Command Parameters," on page 22). * Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) to CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72]) to be compared against all even locations. The CMD[2] signal must be driven to logic 0. Document #: 38-02040 Rev. *F Page 51 of 137
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* Cycle B: The host ASIC continues to drive the CMDV high and applies the command code of Search command (10) on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and hit flag (see page 8 for the description of SSR[0:7]). The DQ[71:0] is driven with 72-bit data ([71:0]), compared to all odd locations. even-numbered GMR of the pair specified by the GMR Index is used for masking the word in cycle A. The odd-numbered GMR of the pair specified by the GMR Index is used for masking the word in cycle B. The logical 144-bit search operation is shown in Figure 10-29. The entire table of 144-bit entries is compared to a 144-bit word K (presented on the DQ bus in cycles A and B of the command) using the GMR and the local mask bits. The GMR is the 144-bit word specified by the even and odd global mask pair selected by the GMR Index in the command's cycle A. The 144-bit word K (presented on the DQ bus in cycles A and B of the command) is also stored in both even and odd comparand register pairs selected by the Comparand Register Index in the command's cycle B. The two comparand registers can subsequently be used by the Learn command with the even comparand register stored in an even location, and the odd comparand register stored in an adjacent odd location. The word K (presented on the DQ bus in cycles A and B of the command) is compared with each entry in the table starting at location 0. The first matching entry's location address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see "SRAM Addressing" on page 105). Note. The matching address is always going to an even address for a 144-bit Search. 0 143 Even A Location 143 address 0 71 0 2 Comparand Register (even) 4 A 6 Comparand Register (odd) B L GMR K 32766 CFG = 0101010101010101 (144-bit configuration) Figure 10-29. x144 Table with One Device The Search command is a pipelined operation that executes searches at half the rate of the frequency of CLK2X for 144-bit searches in x144-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit Search command cycle (two CLK2X cycles) is shown in Table 10-18. Table 10-18. The Latency of Search from Instruction to SRAM Access Cycle Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 32K x 144 bits 256K x 144 bits 992K x 144 bits Latency in CLK Cycles 4 5 6 Odd B 0
Note. For 144-bit searches, the host ASIC must supply two distinct 72-bit data words on DQ[71:0] during cycles A and B. The
(First matching entry)
For a single device in the table with TLSZ = 00, the latency of the Search from command to SRAM access cycle is 4. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-19. Table 10-19. Shift OF SSF and SSV from SADR HLAT 000 001 010 011 Number of CLK Cycles 0 1 2 3
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Table 10-19. Shift OF SSF and SSV from SADR (continued) HLAT 100 101 110 111 10.6.5 Number of CLK Cycles 4 5 6 7
144-bit Search on Tables Configured as x144 Using up to Eight CYNSE70128 Devices
The hardware diagram of the search subsystem of eight devices is shown in Figure 10-30. The following are parameters programmed into the eight devices. * First seven devices (devices 0-6): CFG = 0101010101010101, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0. * Eighth device (device 7): CFG = 0101010101010101, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1. Note. All eight devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be programmed with LRAM = 1 and LDEV = 1 (device number 7 in this case). All other upstream devices must be programmed with LRAM = 0 and LDEV = 0 (devices 0 through 6 in this case). Figure 10-31 shows the timing diagram for a Search command in the 144-bit-configured table of eight devices for device 0. Figure 10-32 shows the timing diagram for a Search command in the 144-bit-configured table consisting of eight devices for device number 1. Figure 10-33 shows the timing diagram for a Search command in the 144-bit configured table consisting of eight devices for device number 7 (the last device in this specific table). For these timing diagrams, four 144-bit searches are performed sequentially, and the following Hit/Miss assumptions were made (see Table 10-20). Table 10-20. Hit/Miss Assumption Search Number Device 0 Device 1 Device 2-6 Device 7 1 Hit Miss Miss Miss 2 Miss Hit Miss Miss 3 Hit Hit Miss Hit 4 Miss Miss Miss Hit
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SRAM BHI[2:0] LHO[1] SSF, SSV 6 5 4
CYNSE70128 #0
3 LHI
2
1
0 LHO[0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #1
3 LHI
2
1 LHO[0]
0
DQ[71:0] CMDV CMD[10:0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #2
3 LHI
2 LHO[0]
1
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #3
3 2 LHI LHO[0]
1
0
BHI[2:0]
6
5
CYNSE70128 #4
3 LHI LHO[0]
4
2
1
0
BHI[2:0] 3
21 LHI
0
LHI CYNSE70128 #5 LHO[0]
6
5
4
BHI[2:0] 3
2 1 LHI
0
6 LHO[0]
CYNSE70128 #6
5 4 LHI
BHI[2:0]3
2
1 LHI
0
6
CYNSE70128 #7
54 LHI
BHO[0] BHO[1] BHO[2]
BHO[0] BHO[1] BHO[2]
LHO[1] LHO[0] Figure 10-30. Hardware Diagram for a Table with Eight Devices
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF z z z z z z z 1 1 z z 1 1 z z A1 0 0 1 z z z z A3 0 0 1 z z z z 0 01 Search3 01 01 01 Search2 Search4
A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0. Note: |(LHI[6:0]) stands for the boolean `OR' of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3 (This (This device device is the is the global global winner.) winner.) Search2 Search4 (Miss (Miss on this on this device.) device.)
Figure 10-31. Timing Diagram for 144-bit Search Device Number 0
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ LHI[6:0] LHO[1:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF z z z z z z z 1 1 z z A2 0 0 1 z z z 01 Search3 01 01 01 Search2 Search4
A B AB A BAB A B AB A BAB D1 D2 D3 D4
Search3 (Local winner but not global winner.) CFG = 0101010101010101, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0. Search2 Search4 Note: |(LHI[6:0]) stands for the boolean `OR' of the entire bus LHI[6:0]. (Miss (This Note: Each bit in LHO[1:0] is the same logical signal. deviceis on this device.) global winner.) Figure 10-32. Timing Diagram for 144-bit Search Device Number 1
Search1 (Miss on this device.)
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 1 0 0 0 z z 1 1 0 0 z z A4 0 0 1 01 Search3 01 01 01 Search2 Search4
A B AB A BAB A B AB A BAB D1 D2 D3 D4
z
CFG = 0101010101010101, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1. Note: |(LHI[6:0]) stands for the boolean `OR' of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3 (Local but not (Miss on this device) global winner) Search2 Search4 (Miss on (Global this device) winner.)
Figure 10-33. Timing Diagram for 144-bit Search Device Number 7 (Last Device) The following is the sequence of operation for a single 144-bit Search command (also see "Commands and Command Parameters" on page 22). * Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same bits that will be driven by this device on SADR[23:21] if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72]) in order to be compared against all even locations. The CMD[2] signal must be driven to a logic 0. * Cycle B: The host ASIC continues to drive CMDV high and to apply the command code for Search command (10) on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles A and B. CMD[8:6] signals must be driven with the SSR index that will be used for storing the address of the matching entry and the hit flag (see page 8 for the description of SSR[0:7]). The DQ[71:0] is driven with 72-bit data ([71:0]) compared against all odd locations. The logical 144-bit search operation is shown in Figure 10-34. The entire table (eight devices of 144-bit entries) is compared to a 144-bit word K (presented on the DQ bus in cycles A and B of the command) using the GMR and local mask bits. The GMR is the 144-bit word specified by the even and odd global mask pair selected by the GMR Index in the command's cycle A. Document #: 38-02040 Rev. *F Page 57 of 137
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The 144-bit word K (presented on the DQ bus in cycles A and B of the command) is also stored in the even and odd comparand registers specified by the Comparand Register Index in the command's cycle B. In x144 configurations, the even and odd comparand registers can subsequently be used by the Learn command in only one of the devices (the first non-full device). The word K (presented on the DQ bus in cycles A and B of the command) is compared to each entry in the table starting at location 0. The first matching entry's location, address L, is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see "SRAM Addressing" on page 105). The global winning device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV = 1 (the default driving device for SSF and SSV signals) will be the default driver for such missed cycles. Note. During 144-bit searches of 144-bit-configured tables, the search hit will always be at an even address. Must be same in each of the eight devices 143 GMR K Even A Odd B 0 0
Location 143 address 0 71 0 2 Comparand Register (even) 4 A 6 Comparand Register (odd) B L
(First matching entry) Will be same in each of the eight devices 262142 CFG = 0101010101010101 (144-bit configuration) Figure 10-34. x144 Table with Eight Devices
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 144-bit searches in x144-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit Search command cycle (two CLK2X cycles) is shown in Table 10-21. Table 10-21. Search Latency from Instruction to SRAM Access Cycle Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 32K x 144 bits 256K x 144 bits 992K x 144 bits Latency in CLK Cycles 4 5 6
For one to eight devices in the table and TLSZ = 01, the latency of a Search from command to SRAM access cycle is 5. In addition, SSV and SSF shift further to the right for different values of HLAT as specified in Table 10-22. Table 10-22. Shift OF SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7
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10.6.6 144-bit Search on Tables Configured as x144 Using up to 31 CYNSE70128 Devices The hardware diagram of the search subsystem of 31 devices is shown in Figure 10-35. Each of the four blocks in the diagram represents a block of eight CYNSE70128 devices (except the last, which has seven devices). The diagram for a block of eight devices is shown in Figure 10-36. Following are the parameters programmed into the 31 devices. * First thirty devices (devices 0-29): CFG = 0101010101010101, TLSZ = 10, HLAT = 001, LRAM = 0, and LDEV = 0. * Thirty-first device (device 30): CFG = 0101010101010101, TLSZ = 10, HLAT = 001, LRAM = 1, and LDEV = 1. Note. All 31 devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case). The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 10-23. For the purpose of illustrating timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. Figure 1037 shows the timing diagram for a Search command in the 144-bit-configured table (31 devices) for each of the eight devices in block number 0. Figure 10-38 shows the timing diagram for Search command in the 72-bit-configured table (31 devices) for all the devices in block number 1 above the winning device in that block. Figure 10-39 shows the timing diagram for the globally winning device (the final winner within its own block and all blocks) in block number 1. Figure 10-40 shows the timing diagram for all the devices below the globally winning device in block number 1. Figure 10-41, Figure 10-42, and Figure 10-43 respectively show the timing diagrams of the devices above globally winning device, the globally winning device and devices below the globally winning device for block number 2. Figure 10-44, Figure 10-45, Figure 10-46, and Figure 10-47 respectively show the timing diagrams of the devices above the globally winning device, the globally winning device, and devices below the globally winning device except the last device (device 30), and the last device (device 30) for block number 3. The 144-bit Search operation is pipelined and executes as follows. Four cycles from the Search command, each of the devices knows the outcome internal to it for that operation. In the fifth cycle after the Search command, the devices in a block (being less than or equal to eight devices resolving the winner within them using the LHI[6:0] and LHO[1:0] signalling mechanism) arbitrate for a winner amongst them. In the sixth cycle after the Search command, the blocks (of devices) resolve the winning block through the BHI[2:0] and BHO[2:0] signalling mechanism. The winning device in the winning block is the global winning device for a Search operation. Table 10-23. Hit/Miss Assumption Search Number Block 0 Block 1 Block 2 Block 3 1 Miss Miss Miss Hit 2 Miss Miss Hit Hit 3 Miss Hit Hit Miss 4 Miss Miss Miss Miss
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BHI[2] SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70128s Block 0 (devices 0-7) BHO[1] BHO[0] BHO[2]
SRAM
GND Block of 8 CYNSE70128s Block 1 (devices 8-15) BHO[2] BHO[1] BHO[0]
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BHI[2]
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Block of 8 CYNSE70128s Block 2 (devices 16-23) BHO[2] BHO[1] BHO[0]
BHI[1] BHI[0] BHI[2] Block of 7 CYNSE70128s Block 3 (devices 24-30) DQ[71:0] BHO[2] BHO[1] BHO[0] CMD[10:0], CMDV Figure 10-35. Hardware Diagram for a Table with 31 Devices
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SRAM BHI[2:0] LHO[1] 6 5 4
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3 LHI
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0 LHO[0]
BHI[2:0] DQ[71:0] CMDV CMD[10:0] SSV, SSF LHO[1]
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LHI CYNSE70128 #5 LHO[0]
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5 LHI
4 BHO[0] BHO[1] BHO[2] LHO[1] LHO[0]
BHO[0] BHO[1] BHO[2]
Figure 10-36. Hardware Diagram for a Block of up to Eight Devices
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-37. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device)
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Figure 10-38. Timing Diagram for Each Device Above the Winning Device in Block Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) 1 1 z zz A3 0 0 1 z z z z 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (This device global winner.) Search2 Search4 (Miss (Miss on this on this device.) device.)
Figure 10-39. Timing Diagram for Globally Winning Device in Block Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0] stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI(6:0) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) Figure 10-40. Timing Diagram for Devices Below the Winning Device in Block Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-41. Timing Diagram for Devices Above the Winning Device in Block Number 2
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z 0 z z z z z Search1 (Miss on this device.) 1 1 z z 0 1 A2 z z z z 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (Hit But not winner.) Search2 Search4 (Miss (Global winner.) on this device.)
Figure 10-42. Timing Diagram for Globally Winning Device in Block Number 2
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 Search4 (Miss on (Miss on this this device.) device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-43. Timing Diagram for Devices Below the Winning Device in Block Number 2
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 Search4 (Miss (Miss on this on this device.) device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-44. Timing Diagram for Devices Above the Winning Device in Block Number 3
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z 0 z 0 z z z z 1 1 Search1 (Global winner.) z z Search3 (Miss on this device.) Search2 Search4 (Miss (Hit on this but not device.) global winner.) 1 A1 z z z z 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-45. Timing Diagram for Globally Winning Device in Block Number 3
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 Search4 (Miss on (Miss on this this device.) device.) 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-46. Timing Diagram for Devices Below the Winning Device in Block Number 3 Except Device 30 (the Last Device)
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV Search1 CMD[1:0] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 1 0 0 0 z z 1 0 0 0 0 0 z z z 0 0 1 01 Search3 01 01 01 Search2 Search4 A B AB A BAB A B AB A BAB D1 D2 D3 D4
z
CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1. Note: |(BHI[2:0)] stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3 (Hit (Hit on on some some device device above.) above.) Search4 Search2 (Global (Hit on miss; this device some default device driver.) above.)
Figure 10-47. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) The following is the sequence of operation for a single 144-bit Search command (also refer to "Command and Command Parameters," on page 22). * Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72]) in order to be compared against all even locations. The CMD[2] signal must be driven to logic 0.
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* Cycle B: The host ASIC continues to drive the CMDV high and to apply Search command code (10) on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ bus during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag (see page 16 for the description of SSR[0:7]). The DQ[71:0] is driven with 72-bit data ([71:0])to be compared against all odd locations. The logical 144-bit search operation is as shown in Figure 10-48. The entire table of 31 devices (consisting of 144-bit entries) is compared against a 144-bit word K that is presented on the DQ bus in cycles A and B of the command using the GMR and local mask bits. The GMR is the 144-bit word specified by the even and odd global mask pair selected by the GMR Index in the command's cycle A. The 144-bit word K that is presented on the DQ bus in cycles A and B of the command is also stored in the even and odd comparand registers specified by the Comparand Register Index in the command's cycle B. In x144 configurations, the even and odd comparand registers can subsequently be used by the Learn command in only the first non-full device. Note. The Learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one block. The word K that is presented on the DQ bus in cycles A and B of the command is compared with each entry in the table starting at location 0. The first matching entry's location address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see "SRAM Addressing" on page 105). The global winning device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV = 1 (the default driving device for SSF and SSV signals) will be the default driver for such missed cycles. Note. During 144-bit searches of 144bit-configured tables, the search hit will always be at an even address. 0 143 Must be same in each of the 31 devices Even Odd GMR B A K Location 143 address 0 Comparand Register (even) 2 A 4 6 Comparand Register (odd) B 71 0 L (First matching entry) Will be same in each of the 31 1015806 devices CFG = 0101010101010101 (144-bit configuration) 0
Figure 10-48. x144 Table with 31 Devices The Search command is a pipelined operation. It executes a search at half the rate of the frequency of CLK2X for 144-bit searches in x144-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit Search command cycle (two CLK2X cycles) is shown in Table 10-24. Table 10-24. The Latency of Search from Instruction to SRAM Access Cycle Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 32K x 144 bits 256K x 144 bits 992K x 144 bits Latency in CLK Cycles 4 5 6
The latency of a search from command to the SRAM access cycle is 6 for 1-31 devices in the table and where TLSZ = 10. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-25. Table 10-25. Shift OF SSF and SSV from SADR HLAT 000 001 010 011 Document #: 38-02040 Rev. *F Number of CLK Cycles 0 1 2 3 Page 73 of 137
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Table 10-25. Shift OF SSF and SSV from SADR (continued) HLAT 100 101 110 111 10.6.7 Number of CLK Cycles 4 5 6 7
288-bit Search on Tables Configured as x288 Using a Single CYNSE70128 Device
Figure 10-49 shows the timing diagram for a Search command in the 288-bit-configured table (CFG = 1010101010101010) consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this search subsystem is shown in Figure 10-50. cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 1 1 1 0 0 0 A B AB A BAB A B CD A BCD D2 D1 A1 0 0 1 0 1 1 1 0 1 1 0 1 0 Search2 Miss 0 Search1 01 Search2 01
CFG = 1010101010101010, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1.
Search1 Hit
Figure 10-49. Timing Diagram for 288-bit Search (One Device)
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BHO[2:0]
LHO[1]
Figure 10-50. Hardware Diagram for a Table with One Device The following is the sequence of operation for a single 144-bit Search command (also refer to "Commands and Command Parameters" on page 22). * Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair used for bits [287:144] of the data being searched. DQ[71:0] must be driven with the 72-bit data ([287:216]) to be compared to all locations 0 in the four 72-bits-word page. The CMD[2] signal must be driven to logic 1. Note. CMD[2] = 1 signals that the Search is a x288-bit search. CMD[8:3] in this cycle is ignored. * Cycle B: The host ASIC continues to drive the CMDV high and continues to apply the command code of Search command (10) on CMD[1:0]. The DQ[71:0] is driven with the 72-bit data ([215:144]) to be compared to all locations 1 in the four 72-bitsword page. * Cycle C: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair used for bits [143:0] of the data being searched. CMD[8:6] signals must be driven with the bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72]) to be compared to all locations 2 in the four 72-bits-word page. The CMD[2] signal must be driven to logic 0. * Cycle D: The host ASIC continues to drive the CMDV high and applies Search command code (10) on CMD[1:0]. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag (see page 8 for the description of SSR[0:7]). The DQ[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locations 3 in the four 72-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x288 tables.
Note. For 288-bit searches, the host ASIC must supply four distinct 72-bit data words on DQ[71:0] during cycles A, B, C, and D. The GMR index in cycle A selects a pair of GMRs that apply to DQ data in cycles A and B. The GMR index in cycle C selects a pair of GMRs that apply to DQ data in cycles C and D.
The logical 288-bit Search operation is shown in Figure 10-51. The entire table of 288-bit entries is compared to a 288-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the 288-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command's cycles A and C. The 288-bit word K that is presented on the DQ bus in cycles A, B, C and D of the command is compared with each entry in the table starting at location 0. The first matching entry's location address L is the winning address that is driven as part of the SRAM address on SADR[23:0] lines (see "SRAM Addressing" on page 105). Note. The matching address is always going to be location 0 in a fourentry page for a 288-bit Search (two LSBs of the matching index will be 00). 0 287 0 GMR A K Location 287 address 0 4 8 12 1 B 2 C 3 D 0
L (First matching entry) 16380 CFG = 1010101010101010 (288-bit configuration) Figure 10-51. x288 Table with One Device
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The Search command is a pipelined operation and executes at one-fourth the rate of the frequency of CLK2X for 288-bit searches in x288-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 288-bit Search command (measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-26. Table 10-26. The Latency of Search from Cycles C and D to SRAM Access Cycle Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 16K x 288 bits 128K x 288 bits 496K x 288 bits Latency in CLK Cycles 4 5 6
The latency of a Search from command to SRAM access cycle is 4 for only a single device in the table and TLSZ = 00. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-27. Table 10-27. Shift OF SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 10.6.8 Number of CLK Cycles 0 1 2 3 4 5 6 7
288-bit Search on Tables Configured as x288 Using up to Eight CYNSE70128 Devices
The hardware diagram of the search subsystem of eight devices is shown in Figure 10-52. The following are the parameters programmed in the eight devices. * First seven devices (devices 0-6): CFG = 1010101010101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0. * Eighth device (device 7): CFG = 1010101010101010, TLSZ = 01, HLAT = 000, LRAM = 1, and LDEV = 1. Note. All eight devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be programmed with LRAM = 1 and LDEV = 1 (device number 7 in this case). All other upstream devices must be programmed with LRAM = 0 and LDEV = 0 (devices 0 through 6 in this case). Figure 10-53 shows the timing diagram for a Search command in the 288-bit-configured table of eight devices for device number 0. Figure 10-54 shows the timing diagram for a Search command in the 288-bit-configured table of eight devices for device number 1. Figure 10-55 shows the timing diagram for a Search command in the 288-bit-configured table of eight devices for device number 7 (the last device in this specific table). For these timing diagrams three 288-bit searches are performed sequentially. The following Hit/Miss assumptions were made as shown in Table 10-28. Table 10-28. Hit/Miss Assumption Search Number Device 0 Device 1 Device 2-6 Device 7 1 Hit Miss Miss Miss 2 Miss Hit Miss Miss 3 Miss Miss Miss Miss
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SRAM BHI[2:0] LHO[1] SSF, SSV 6 5 4
CYNSE70128 #0
3 LHI
2
1
0 LHO[0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #1
3 LHI
2
1 LHO[0]
0
DQ[71:0] CMDV CMD[10:0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #2
3 LHI
2 LHO[0]
1
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #3
3 2 LHI LHO[0]
1
0
BHI[2:0]
6
5
CYNSE70128 #4
3 LHI LHO[0]
4
2
1
0
BHI[2:0] 3
21 LHI
0
LHI CYNSE70128 #5 LHO[0]
6
5
4
BHI[2:0] 3
2 1 LHI
0
6 LHO[0]
CYNSE70128 #6
5 4 LHI
BHI[2:0]3
2
1 LHI
0
6
CYNSE70128 #7
54 LHI
BHO[0] BHO[1] BHO[2] LHO[1] LHO[0]
BHO[0] BHO[1] BHO[2]
Figure 10-52. Hardware Diagram for a Table with Eight Devices
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF z z z z z z z 1 1 z z A1 0 0 1 z z z z 0 A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
Search1 CFG = 1010101010101010, HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0. (This device Note: |(LHI[6:0]) stands for the boolean `OR' of the entire bus LHI[6:0]. is the Note: Each bit in LHO[1:0] is the same logical signal. global winner.)
Search2 (Miss on this device.)
Search3 (Miss on this device.)
Figure 10-53. Timing Diagram for 288-bit Search Device Number 0
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF z z z A2 0 0 1 z A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
z z z z Search1 (Miss on this device.)
z
1 1
z z
CFG = 1010101010101010, HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0. Note: |(LHI[6:0]) stands for the boolean `OR' of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (Miss on this device.) Search2 (This device is global winner.)
Figure 10-54. Timing Diagram for 288-bit Search Device Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] SADR[23:0] CE_L ALE_L 0 0 1 0 0 0 z z 0 0 z z 0 0 1 0 1 z z z z z 0 0 1 A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1
Search1 01
Search2 01
Search3 01
WE_L OE_L SSV SSF
z
CFG = 1010101010101010, HLAT = 000, TLSZ = 01, LRAM = 1, LDEV = 1. Note: |(LHI[6:0]) stands for the boolean `OR' of the entire bus LHI[6:0]. Note: Each bit in LHO[1:0] is the same logical signal.
Search1 (Miss on this device.)
Search2 Search3 (Global (Miss miss.) on this device.)
Figure 10-55. Timing Diagram for 288-bit Search Device Number 7 (Last Device) The following is the sequence of operation for a single 288-bit Search command (also see "Commands and Command Parameters" on page 22). * Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair used for bits [287:144] of the data being searched in this operation. DQ[71:0] must be driven with the 72-bit data ([287:216]) to be compared against all locations 0 in the four-word 72bit page. The CMD[2] signal must be driven to logic 1. Note. CMD[2] = 1 signals that the search is a 288-bit search. CMD[8:3] in this cycle is ignored. * Cycle B: The host ASIC continues to drive the CMDV high and applies Search command code (10) on CMD[1:0]. The DQ[71:0] is driven with the 72-bit data ([215:144]) to be compared against all locations 1 in the four 72-bits-word page. * Cycle C: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair used for bits [143:0] of the data being searched. CMD[8:6] signals must be driven with the bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven
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with the 72-bit data ([143:72]) to be compared against all locations 2 in the four 72-bits-word page. The CMD[2] signal must be driven to logic 0. * Cycle D: The host ASIC continues to drive the CMDV high and applies Search command code (10) on CMD[1:0]. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag (see page 16 for the description of SSR[0:7]). The DQ[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locations 3 in the four 72-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x288 tables.
Note. For 288-bit searches, the host ASIC must supply four distinct 72-bit data words on DQ[71:0] during cycles A, B, C, and D.
The GMR index in cycle A selects a pair of GMRs in each of the eight devices that apply to DQ data in cycles A and B. The GMR index in cycle C selects a pair of GMRs in each of the eight devices that apply to DQ data in cycles C and D.
The logical 288-bit Search operation is shown in Figure 10-56. The entire table of 288-bit entries is compared to a 288-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and the local mask bits. The GMR is the 288-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command's cycles A and C in each of the eight devices. The 288-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to each entry in the table starting at location 0. The first matching entry's location address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see "SRAM Addressing" on page 105). Note. The matching address is always going to be a location 0 in a four-entry page for 288-bit Search (two LSBs of the matching index will be 00). 287 GMR K 0 A 1 B 2 C 3 D 0 0 Must be same in each of the eight devices
Location 287 address 0 4 8 12
L (First matching entry) 131068 CFG = 1010101010101010 (288-bit configuration) Figure 10-56. x288 Table with Eight Devices The Search command is a pipelined operation and executes search at one-fourth the rate of the frequency of CLK2X for 288-bit searches in x288-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 288-bit Search command (measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-29. Table 10-29. The Latency of Search from Cycles C and D to SRAM Access Cycle Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 16K x 288 bits 128K x 288 bits 496K x 288 bits Latency in CLK Cycles 4 5 6
The latency of search from command to SRAM access cycle is 5 for only a single device in the table and TLSZ = 01. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-30. Table 10-30. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 Document #: 38-02040 Rev. *F Number of CLK Cycles 0 1 2 3 4 Page 81 of 137
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Table 10-30. Shift of SSF and SSV from SADR HLAT 101 110 111 10.6.9 Number of CLK Cycles 5 6 7
288-bit Search on Tables Configured as x288 Using up to 31 CYNSE70128 Devices
The hardware diagram of the search subsystem of 31 devices is shown in Figure 10-57. Each of the four blocks in the diagram represents a block of eight CYNSE70128 devices, except the last which has seven devices. The diagram for a block of eight devices is shown in Figure 10-58. The following are the parameters programmed into the 31 devices. * First thirty devices (devices 0-29): CFG = 1010101010101010, TLSZ = 10, HLAT = 000, LRAM = 0, and LDEV = 0. * Thirty-first device (device 30): CFG = 1010101010101010, TLSZ = 10, HLAT = 000, LRAM = 1, and LDEV = 1. Note. All 31 devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case). The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 10-31. For the purpose of illustrating the timings, it is further assumed that there is only one device with the matching entry in each block. Figure 10-59 shows the timing diagram for a Search command in the 288-bit-configured table consisting of 31 devices for each of the eight devices in block number 0. Figure 10-60 shows the timing diagram for a Search command in the 288-bit-configured table of 31 devices for all devices above the winning device in block number 1. Figure 10-61 shows the timing diagram for the globally winning device (the final winner within its own and all blocks) in block number 1. Figure 10-62 shows the timing diagram for all the devices below the globally winning device in block number 1. Figure 10-63, Figure 10-64, and Figure 10-65, respectively, show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winning device for block number 2. Figure 10-66, Figure 10-67, Figure 10-68, and Figure 10-69, respectively, show the timing diagrams of the device above the globally winning device, the globally winning device, the devices below the globally winning device (except device 30), and last device (device 30) for block number 3. The 288-bit Search operation is pipelined and executes as follows. Four cycles from the last cycle of the Search command each of the devices knows the outcome internal to it for that operation. In the fifth cycle from the Search command, the devices in a block (which is less than or equal to eight devices resolving the winner within them using an LHI[6:0] and LHO[1:0] signalling mechanism) arbitrate for a winner. In the sixth cycle after the Search command, the blocks of devices resolve the winning block through a BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device for the Search operation. Table 10-31. Hit/Miss Assumption Search Number Block 0 Block 1 Block 2 Block 3 1 Miss Miss Miss Hit 2 Miss Miss Hit Hit 3 Miss Hit Hit Miss
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BHI[2] SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70128s block 0 (devices 0-7) BHO[1] BHO[0] BHO[2]
SRAM
GND Block of 8 CYNSE70128s block 1 (devices 8-15) BHO[2] BHO[1] BHO[0]
BHI[2]
BHI[1]
BHI[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70128s block 2 (devices 16-23) BHO[2] BHO[1] BHO[0]
BHI[1] BHI[0] BHI[2] Block of 7 CYNSE70128s block 3 (devices 24-30) BHO[2] BHO[1] BHO[0] CMD[10:0], CMDV DQ[71:0]
Figure 10-57. Hardware Diagram for a Table with 31 Devices
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BHI[2:0] SRAM BHI[2:0] LHO[1] 6 5 4
CYNSE70128 #0
3 LHI
2
1
0 LHO[0]
BHI[2:0] DQ[71:0] CMDV CMD[10:0] SSV, SSF LHO[1]
6
5
4
CYNSE70128 #1
3 LHI
2
1 LHO[0]
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #2
3 LHI
2 LHO[0]
1
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #3
3 2 LHI LHO[0]
1
0
BHI[2:0]
6
5
CYNSE70128 #4
3 LHI LHO[0]
4
2
1
0
BHI[2:0] 3
21 LHI
0
LHI CYNSE70128 #5 LHO[0]
6
5
4
BHI[2:0] 3
2 1 LHI
0
6 LHO[0]
CYNSE70128 #6
5 4 LHI
BHI[2:0]3
2
1 LHI
0
6
CYNSE70128 #7
5 LHI
4 BHO[0] BHO[1] BHO[2] LHO[1] LHO[0]
BHO[0] BHO[1] BHO[2]
Figure 10-58. Hardware Diagram for a Block of up to Eight Devices
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 Search3 (Misson (Misson this device.)Search2 this device) (Miss on this device.) A B AB A BABA BAB A B C D A BC DA BC D D2 D1 D3 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-59. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device)
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 (Miss on this device.) A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-60. Timing Diagram for Each Device Above the Winning Device in Block Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) 1 1 Search3 (This device Search2 global (Miss on winner.) this device.) A3 0 0 1 A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-61. Timing Diagram for Globally Winning Device in Block Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device.) Search2 (Miss on this device.) A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-62. Timing Diagram for Devices Below the Winning Device in Block Number 1
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search3 (Miss on this device; hit in block 0 Search2 or block 1.) (Miss on this device.) A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-63. Timing Diagram for Devices Above the Winning Device in Block Number 2
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF z z z z Search1 (Miss on this device.) Search2 (Global winner.) 1 1 z z Search3 (Hit but not winner.) 0 0 0 0 z z z z z z A2 0 0 1 z z z z A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-64. Timing Diagram for Globally Winning Device in Block Number 2
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (Miss on this device.) A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-65. Timing Diagram for Devices Below the Winning Device in Block Number 2
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (Miss on this device.) A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-66. Timing Diagram for Devices Above the Winning Device in Block Number 3
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z 1 1 Search1 (Global winner.) Search2 (Hit but not global winner.) z z Search3 (Miss on this device.) A1 0 0 1 z z z z A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Figure 10-67. Timing Diagram for Globally Winning Device in Block Number 3
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0]) LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search (Miss on this device.) Search3 (Miss on this device.) A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0] Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0] Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search2 (Miss on this device.)
Figure 10-68. Timing Diagram for Devices Below the Winning Device in Block Number 3 Except Device 30 (the Last Device)
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0)] LHO[1:0] I(BHI[2:0]) BHO[2:0] SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 1 0 0 0 z z Search1 (Hit on some device above.) 0 0 z z 0 0 0 0 0 0 z z z z 0 0 1 z z z 0 0 1 A B AB A BABA BAB A B CD A BC DA BC D D3 D2 D1 Search1 01 Search2 01 Search3 01
z
CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 1, LDEV = 1. Note: |(BHI[2:0]) stands for the boolean `OR' of the entire bus BHI[2:0]. Note: |(LHI[6:0]) stands for the boolean `OR' for the entire bus LHI[6:0]. Note: Each bit in BHO[2:0] is the same logical signal. Note: Each bit in LHO[1:0] is the same logical signal.
Search3 (Hit on some device Search2 above.) (Hit on some device above.) Figure 10-69. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table)
The following is the sequence of operation for a single 288-bit Search command (also refer to "Commands and Command Parameters" on page 22). * Cycle A: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair used for bits [287:144] of the data being searched. DQ[71:0] must be driven with the 72-bit data ([287:216])to be compared to all locations 0 in the four 72-bits-word page. The CMD[2] signal must be driven to logic 1. Note. CMD[2] = 1 signals that the search is a x288-bit search. CMD[8:6] is ignored in this cycle. * Cycle B: The host ASIC continues to drive the CMDV high and applies Search command (10) on CMD[1:0]. The DQ[71:0] is driven with the 72-bit data ([215:144]) to be compared to all locations 1 in the four 72-bits-word page.
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* Cycle C: The host ASIC drives the CMDV high and applies Search command code (10) on CMD[1:0] signals. {CMD[10], CMD[5:3]} signals must be driven with the index to the GMR pair used for the bits [143:0] of the data being searched. CMD[8:6] signals must be driven with the bits that will be driven by this device on SADR[23:21] if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72]) to be compared to all locations 2 in the four 72-bits-word page. The CMD[2] signal must be driven to logic 0. * Cycle D: The host ASIC continues to drive the CMDV high and continues to apply Search command code (10) on CMD[1:0]. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag (see page 16 for a description of SSR[0:7]). The DQ[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locations 3 in the four 72-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x288 tables.
Note. For 288-bit searches, the host ASIC must supply four distinct 72-bit data words on DQ[71:0] during cycles A, B, C, and D.
The GMR Index in cycle A selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles A and B. The GMR Index in cycle C selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles C and D.
The logical 288-bit Search operation is as shown in Figure 10-70. The entire table of 288-bit entries is compared to a 288-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the 288-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command's cycles A and C in each of the 31 devices. The 288-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to each entry in the table starting at location 0. The first matching entry's location address L is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see see "SRAM Addressing" on page 105). Note. The matching address is always going to be location 0 in a four-entry page for 288-bit search (two LSBs of the matching index will be 00). 0 287 GMR K 0 A 1 B 2 C 3 D 0 Must be same in each of the 31 devices
Location 287 address 0 4 8 12
L (First matching entry) 507900 CFG = 1010101010101010 (288-bit configuration) Figure 10-70. x288 Table with 31 Devices The Search command is a pipelined operation and executes a search at one-fourth the rate of the frequency of CLK2X for 288bit searches in x288-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 288-bit Search command (measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-32. Table 10-32. The Latency of Search from Cycles C and D to SRAM Access Cycle Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 16K x 288 bits 128K x 288 bits 496K x 288 bits Latency in CLK Cycles 4 5 6
The latency of a Search from command to SRAM access cycle is 6 for only a single device in the table and TLSZ = 10. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-33. Table 10-33. Shift of SSF and SSV from SADR HLAT 000 001 010 011 Document #: 38-02040 Rev. *F Number of CLK Cycles 0 1 2 3 Page 96 of 137
CYNSE70128
Table 10-33. Shift of SSF and SSV from SADR (continued) HLAT 100 101 110 111 Number of CLK Cycles 4 5 6 7
10.6.10 Mixed-Size Searches on Tables Configured with Different Widths Using a CYNSE70128 with CFG_L LOW This subsection will cover mixed searches (x72, x144, and x288) with tables of different widths (x72, x144, x288). The sample operation shown is for a single device with CFG = 1010010100000000 containing three tables of x72, x144, and x288 widths. The operation can be generalized to a block of 8-31 devices using four blocks; the timing and the pipeline operation is the same as described previously for fixed searches on a table of one-width-size. Figure 10-71 shows three sequential searches: first, a 72-bit search on the table configured as x72, then a 144-bit search on a table configured as x144, and finally a 288-bit search on the table configured as x288 bits that each results in a hit. Note. The DQ[71:70] will be 00 in each of the two A and B cycles of the x72-bit search (Search1). DQ[71:70] is 01 in each of the A and B cycles of the x144-bit search (Search2). DQ[71:70] is 10 in each of the A, B, C, and D cycles of the x288-bit search (Search3). By having table designation bits, the CYNSE70128 enables the creation of many tables in a bank of NSEs of different widths. Figure 10-72 shows the sample table. Two bits in each 72-bit entry will need to designated as the table number bits. One example choice can be the 00 values for the table configured as x72, 01 values for tables configured as x144, and 10 values for tables configured as x288. For the above explanation, it is further assumed that bits [71:70] for each entry will be designed as such table designation bits. cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[2] CMD[10:2] A B AB A BAB A B A B A BCD D3 D1 D2 A1 1 1 1 0 0 0 A2 0 0 1 0 1 0 1 1 0 0 1 1 0 0 A3 1 1 0 0 1 1 Search1 Search3 01 01 01 Search2
DQ SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF
Search2 CFG = 1010101010101010, HLAT = 010, TLSZ = 00, LRAM = 1, LDEV = 1. Search2 Search1 x144 Hit x288 Hit x72 Hit Figure 10-71. Timing Diagram for Mixed Search (One Device)
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72 32 K 8K 4K 144 288
CFG = 10 10 01 01 00 00 00 00 Figure 10-72. Multiwidth Configurations Example 10.6.11 Mixed-Size Searches on Tables Configured to Different Widths Using a CYNSE70128 with CFG_L HIGH This subsection will cover the mixed-size searches (x72, x144, and x288) with tables of different widths (x72, x144, x288) with CFG_L set high. The previous subsection described searches on tables of different widths using table designation bits in the data array. This can be wasteful of the bits in the data array. In order to avoid the waste of these bits and yet support up to three tables of x72, x144, and x288, the CMD[2] and CMD[9] (in CFG_L high mode) in cycle A of the command can be used as shown in Table 10-34. Table 10-34. Searches with CFG_L Set High CMD[9] 0 1 X X CMD[2] 0 0 1 0 Search Search 72-bit-configured partitions only. Search 144-bit-configured partitions only. Cycles A and B for searching 288-bit-configured partitions. Cycles C and D for searching 288-bit-configured partitions.
10.7
LRAM and LDEV Description
When NSEs are cascaded using multiple CYNSE70128s, the SADR, CE_L, and WE_L (three-state signals) are all tied together. In order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For non-Search or non-Learn cycles (see "Learn Command" on page 98) or search cycles with a global miss, the SADR, CE_L, and WE_L signals are driven by the device with the LRAM bit set. It is important that only one device in a bank of NSEs that are cascaded have this bit set. Failure to do so will cause contention on SADR, CE_L, WE_L and can potentially cause damage to the device(s). Similarly, when NSEs using multiple CYNSE70128s are cascaded, SSF and SSV (also three-state signals) are tied together. In order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For nonsearch cycles or Search cycles with a global miss the SSF and SSV signals are driven by the device with the LDEV bit set. It is important that only one device in a bank of NSEs that are cascaded together have this bit set. Failure to do so will cause contention on SSV and SSF and can potentially cause damage to the device(s).
10.8
Learn Command
Bit[0] of each 72-bit data location specifies whether an entry in the database is occupied. If all the entries in a device are occupied, the device asserts FULO signal to inform the downstream devices that it is full. The result of this communication between depthcascaded devices determines the global FULL signal for the entire table. The FULL signal in the last device determines the fullness of the depth-cascaded table. The device contains 16 pairs of internal, 72-bit-wide comparand registers that store the comparands as the device executes searches. On a miss by the Search signalled to ASIC through the SSV and SSF signals (SSV = 1, SSF = 0), the host ASIC can apply the Learn command to learn the entry from a comparand register to the next-free location (see "NFA Register" on page 19). The NFA updates to the next-free location following each Write or Learn command. In a depth-cascaded table, only a single device will learn the entry through the application of a Learn instruction. The determination of which device is going to learn is based on the FULI and FULO signalling between the devices. The first non-full device learns the entry by storing the contents of the specified comparand registers to the location(s) pointed to by NFA. In a x72-configured table the Learn command writes a single 72-bit location. In a x144-configured table the Learn command writes the next even and odd 72-bit locations. In 144-bit mode, bit[0] of the even and odd 72-bit locations is 0, which indicates that they are cascaded empty, or 1, which indicates that they are occupied.
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The global FULL signal indicates to the table controller (the host ASIC) that all entries within a block are occupied and that no more entries can be learned. The CYNSE70128 updates the signal after each Write or Learn command to a data array. The Learn command generates a Write cycle to the external SRAM, also using the NFA register as part of the SRAM address (see "SRAM Addressing" on page 105). The Learn command is supported on a single block containing up to eight devices if the table is configured either as a x72 or a x144. The Learn command is not supported for x288-configured tables. Additionally, Learn is not supported when the device is operating at > 83-MHz CLK1X (166-MHz CLK2X). Learn is a pipelined operation and lasts for two CLK cycles, as shown in Figure 10-73 where TLSZ = 00, and Figure 10-74 and Figure 10-75 where TLSZ = 01. Figure 10-74 and Figure 10-75 assume that the device performing the Learn operation is not the last device in the table and has its LRAM bit set to 0. Note. The OE_L for the device with the LRAM bit set goes high for two cycles for each Learn (one during the SRAM Write cycle, and one the cycle before). The latency of the SRAM Write cycle from the second cycle of the instruction is shown in Table 10-35. cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X
PHS_L
CMDV
CMD[1:0]
Learn1 X Learn2 X Comp1 Comp2 X 1A 1B X
CMD[10:2]
DQ
z
X
X
X
X
z
SADR[23:0] CE_L WE_L OE_L SSV SSF
z
A1
z
A2
z
1 1 0 0 0 1
0 0
0 0
1 1 0
TLSZ = 00, LRAM = 1, LDEV = 1. Figure 10-73. Timing Diagram of Learn (TLSZ = 00)
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X
PHS_L
CMDV
CMD[1:0]
Learn1 X Learn2 X Comp1 Comp2 X 1A 1B X
CMD[10:2]
DQ
z
X
X
X
X
z
SADR[23:0] CE_L WE_L OE_L SSV SSF z
z
A1
z
A2
z
0 0
0 0
z z z z
TLSZ = 01, LRAM = 0, LDEV = 0. Figure 10-74. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01])
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cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X
PHS_L
CMDV
CMD[1:0]
Learn1 X Learn2 X Comp1 Comp2 X 1A 1B X
CMD[10:2]
DQ
z
X
X
X
X
z
SADR[23:0] CE_L WE_L OE_L SSV SSF
z
z
z
z
1 1 0 0 0 1
z z
1 1
z z
1 1 0
TLSZ = 01, LRAM = 1, LDEV = 1. Figure 10-75. Timing Diagram of Learn on Device Number 7 (TLSZ = 01) Table 10-35. Latency of SRAM Write Cycle from Second Cycle of Learn Instruction Number of Devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) The Learn operation lasts two CLK cycles. The sequence of operation is as follows. * Cycle 1A: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index of the comparand register pair that will be written in the data array in the 144-bit-configured table. For a Learn in a 72-bitconfigured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be driven on SADR[23:21] in the SRAM Write cycle. * Cycle 1B: The host ASIC continues to drive the CMDV to 1, the CMD[1:0] to 11, and the CMD[5:2] with the comparand pair index. CMD[6] must be set to 0 if the Learn is being performed on a 72-bit-configured table, and to 1 if the Learn is being performed on a 144-bit-configured table. Latency in CLK Cycles 4 5 6
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* Cycle 2: The host ASIC drives the CMDV to 0. At the end of cycle 2, a new instruction can begin. The latency of the SRAM Write is the same as the search to the SRAM Read cycle. It is measured from the second cycle of the Learn instruction.
11.0
Depth-Cascading
The NSE application can depth-cascade the devices to various table sizes of different widths (72 bits, 144 bits, or 288 bits). The devices perform all the necessary arbitration to decide which device will drive the SRAM bus. The latency of the searches increases as the table size increases; the Search rate remains constant.
11.1
Depth-Cascading up to Eight Devices (One Block)
Figure 11-1 shows how up to eight devices can be cascaded to form 512K x 72, 256K x 144, or 128K x 288 tables. It also shows the interconnection between the devices for depth-cascading. Each NSE asserts the LHO[1] and LHO[0] signals to inform downstream devices of its result. The LHI[6:0] signals for a device are connected to LHO signals of the upstream devices. The host ASIC must program the TLSZ to 01 for each of up to eight devices in a block. Only a single device drives the SRAM bus in any single cycle.
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SRAM BHI[2:0] LHO[1] SSF, SSV 6 5 4
CYNSE70128 #0
3 LHI
2
1
0 LHO[0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #1
3 LHI
2
1 LHO[0]
0
DQ[71:0] CMDV CMD[10:0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #2
3 LHI
2 LHO[0]
1
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #3
3 2 LHI LHO[0]
1
0
BHI[2:0]
6
5
CYNSE70128 #4
3 LHI LHO[0]
4
2
1
0
BHI[2:0] 3
21 LHI
0
LHI CYNSE70128 #5 LHO[0]
6
5
4
BHI[2:0] 3
2 1 LHI
0
6 LHO[0]
CYNSE70128 #6
5 4 LHI
BHI[2:0]3
2
1 LHI
0
6
CYNSE70128 #7
5 LHI
4 BHO[0] BHO[1] BHO[2]
BHO[0] BHO[1] BHO[2]
LHO[1] LHO[0] Figure 11-1. Depth-Cascading to Form a Single Block
11.2
Depth-Cascading up to 31 Devices (Four Blocks)
Figure 11-2 shows how to cascade up to four blocks. Each block contains up to eight CYNSE70128 devices except the last, and the interconnection within each was shown in the previous subsection with the cascading of up to eight devices in a block. Note. The interconnection between blocks for depth-cascading is important. For each Search, a block asserts BHO[2], BHO[1], and BHO[0]. The BHO[2:0] signals for a block are the signals taken only from the last device in the block. For all other devices within that block, these signals stay open and floating. The host ASIC must program the table size (TLSZ) field to 10 in each of the devices for cascading up to 31 devices (in up to four blocks).
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BHI[2] SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70128s Block 0 (devices 0-7) BHO[1] BHO[0] BHO[2]
SRAM
GND Block of 8 CYNSE70128s Block 1 (devices 8-15) BHO[2] BHO[1] BHO[0]
BHI[2]
BHI[1]
BHI[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70128s Block 2 (devices 16-23) BHO[2] BHO[1] BHO[0]
BHI[1] BHI[0] BHI[2] Block of 7 CYNSE70128s Block 3 (devices 24-30) DQ[71:0] BHO[2] BHO[1] BHO[0] CMD[10:0], CMDV
Figure 11-2. Depth-Cascading Four Blocks
11.3
Depth-Cascading for a FULL Signal
Bit[0] of each of the 72-bit entries is designated as a special bit (1 = occupied; 0 = empty). For each Learn or PIO Write to the data array, each device asserts FULO[1] and FULO[0] if it does not have any empty locations within it (see Figure 11-3). Each device combines the FULO signals from the devices above it with its own full status to generate a FULL signal that gives the full status of the table up to the device asserting the FULL signal. Figure 11-3 shows the hardware connection diagram for generating the FULL signal that goes back to the ASIC. In a depth-cascaded block of up to eight devices, the FULL signal from the last device should be fed back to the ASIC controller to indicate the fullness of the table. The FULL signal of the other devices should be left open. Note. The Learn instruction is supported for only up to eight devices, whereas FULL cascading is allowed only for one block in tables containing more than eight devices. In tables for which a Learn instruction is not going to be used, the bit[0] of each 72bit entry should always be set to 1.
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DQ[71:0] 6 FULO[1] 5
CYNSE70128
VDDQ 43 FULI 2 1 0
FULO[0] FULL 6 5 43 FULI 2 1 0 VDDQ
CYNSE70128
FULO[1]
FULO[0] FULL 6 5 43 FULI 2 1 0 VDDQ
CYNSE70128
FULO[1]
FULO[0] FULL 6 5 43 FULI FULO[0] FULL 6 5 43 FULI FULO[0] FULL VDDQ 4 FULI FULL 2 1 0 VDDQ 2 1 0 VDDQ
CYNSE70128
FULO[1]
CYNSE70128
3
21 FULI
0
6
5
CYNSE70128
FULO[0] VDDQ
3
21 FULI
0
6
CYNSE70128
5
4 FULI FULL
FULO[0]
3
21 FULI
0
6
5
CYNSE70128
4 FULI FULL FULO[1] FULO[0]
Figure 11-3. FULL Generation in a Cascaded Table
12.0
SRAM Addressing
Table 12-1 describes the commands used to generate addresses on the SRAM address bus. The index [15:0] field contains the address of a 72-bit entry that results in a hit in 72-bit-configured quadrant. It is the address of the 72-bit entry that lies at the 144-bit page, and the 288-bit page boundaries in 144-bit- and 288-bit-configured quadrants, respectively. "Registers" on page 15 of this specification, describes the NFA and SSR registers. ADR[15:0] contains the address supplied on the DQ bus during PIO access to the CYNSE70128. Command bits 8, 7, and 6 {CMD[8:6]} are passed from the command to the SRAM address bus. See "Commands" on page 21, for more information. ID[4:0] is the ID of the device driving the SRAM bus (see "Pinout Description" on page 130 for more information).
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12.1 Generating an SRAM BUS Address
Command Search Learn PIO Read PIO Write Indirect Access SRAM Operation Read Write Read Write Write/Read 23 C8 C8 C8 C8 C8 22 C7 C7 C7 C7 C7 21 C6 C6 C6 C6 C6 [20:16] ID[4:0] ID[4:0] ID[4:0] ID[4:0] ID[4:0] [15:0] Index[15:0] NFA[15:0] ADR15:0] ADR[15:0] SSR[15:0]
Table 12-1. SRAM Address
12.2
SRAM PIO Access
The remainder of this section describes SRAM Read and SRAM Write operations. SRAM Read enables Read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will be depend on the value programmed for the TLSZ parameter in the device configuration register. The latency of the ACK from the Read instruction is the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed in the configuration register. Note. SRAM Read is a blocking operation--no new instruction can begin until the ACK is returned by the selected device performing the access. SRAM Write enables Write access to the off-chip SRAM containing associative data. The latency from the second cycle of the Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend on the TLSZ value parameter programmed in the device configuration register. Note. SRAM Write is a pipelined operation--new instruction can begin right after the previous command has ended.
12.3
SRAM Read with a Table of One Device
SRAM Read enables Read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend on the TLSZ value parameter programmed in the device configuration register. The latency of the ACK from the Read instruction is the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed in the configuration register. The following explains the SRAM Read operation in a table with only one device that has the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 12-1 shows the associated timing diagram. For the following description, the selected device refers to the only device in the table because it is the only device to be accessed. * Cycle 1A: The host ASIC applies the Read instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[23:21] on CMD[8:6]. * Cycle 1B: The host ASIC continues to apply the Read instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set to 10 to select the SRAM address. * Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition. * Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition. * Cycle 4: The selected device starts to drive DQ[71:0] and drives ACK from high-Z to low. * Cycle 5: The selected device drives the Read address on SADR[23:0]; it also drives ACK high, CE_L low, and ALE_L low. * Cycle 6: The selected device drives CE_L high, ALE_L high, the SADR bus, the DQ bus in a three-state condition, and ACK low. At the end of cycle 6, the selected device floats ACK in a three-state condition, and a new command can begin.
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CYNSE70128
cycle 1 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] Read A B z z cycle 2 cycle 3 cycle 4 cycle 5 cycle 6
DQ OE_L WE_L CE_L ALE_L SADR 0 1 1 1 z
Address
0 0 Address
1 1 z
ACK SSV SSF
z 0 0
0
1
0
z
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1.
DQ driven by CYNSE70128
Figure 12-1. SRAM Read Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
12.4
SRAM Read with a Table of up to Eight Devices
The following explains the SRAM Read operation completed through a table of up to eight devices using the following parameters: TLSZ = 01. Figure 12-2 diagrams a block of eight devices. The following assumes that SRAM access is successfully achieved through CYNSE70128 device number 0. Figure 12-3 and Figure 12-4 show timing diagrams for device number 0 and device number 7, respectively. * Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. During this cycle the host ASIC also supplies SADR[23:21] on CMD[8:6]. * Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with DQ[20:19] set to 10 to select the SRAM address. * Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition. * Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition. * Cycle 4: The selected device starts to drive DQ[71:0]. * Cycle 5: The selected device continues to drive DQ[71:0] and drives ACK from high-Z to low. * Cycle 6: The selected device drives the Read address on SADR[23:0]. It also drives ACK high, CE_L low, WE_L high, and ALE_L low. * Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and DQ bus in a three-state condition. It continues to drive ACK low. At the end of cycle 7, the selected device floats ACK in three-state condition and a new command can begin. Document #: 38-02040 Rev. *F Page 107 of 137
CYNSE70128
SRAM BHI[2:0] LHO[1] SSF, SSV 6 5 4
CYNSE70128 #0
3 LHI
2
1
0 LHO[0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #1
3 LHI
2
1 LHO[0]
0
DQ[71:0] CMDV CMD[10:0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #2
3 LHI
2 LHO[0]
1
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #3
3 2 LHI LHO[0]
1
0
BHI[2:0]
6
5
CYNSE70128 #4
3 LHI LHO[0]
4
2
1
0
BHI[2:0] 3
21 LHI
0
LHI CYNSE70128 #5 LHO[0]
6
5
4
BHI[2:0] 3
2 1 LHI
0
6 LHO[0]
CYNSE70128 #6
5 4 LHI
BHI[2:0]3
2
1 LHI
0
6
CYNSE70128 #7
54 LHI
BHO[0] BHO[1] BHO[2]
BHO[0] BHO[1] BHO[2]
LHO[1] LHO[0] Figure 12-2. Table of a Block of Eight Devices
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CYNSE70128
cycle 1 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ OE_L WE_L CE_L ALE_L SADR z z z 0 z z z SSV SSF 0 z z DQ Driven by Selected CYNSE70128 0 Address 1 0 z 1 z z A Read B z z cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7
Address
TLSZ = 01, HLAT = 000, LRAM = 0, LDEV = 0.
Figure 12-3. SRAM Read Through Device Number 0 in a Block of Eight Devices
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CYNSE70128
cycle 1 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ OE_L WE_L CE_L ALE_L SADR ACK SSV SSF 0 1 1 1 z z z z z z z z 1 1 1 A Read B z cycle 2 cycle 3 cycle 4 cycle 5 cycle 6
Address
TLSZ = 01, HLAT = 000, LRAM = 1, LDEV = 1.
Figure 12-4. SRAM Read Timing for Device Number 7 in a Block of Eight Devices
12.5
SRAM Read with a Table of up to 31 Devices
The following explains the SRAM Read operation accomplished through a table of up to 31 devices, using the following parameters: TLSZ = 10. The diagram of such a table is shown in Figure 12-5. The following assumes that SRAM access is being accomplished through CYNSE70128 device number 0, that device number 0 is the selected device. Figure 12-6 and Figure 127 show the timing diagrams for device number 0 and device number 30, respectively. * Cycle 1A: The host ASIC applies the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[23:21] on CMD[8:6]. * Cycle 1B: The host ASIC continues to apply the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with DQ[20:19] set to 10, to select the SRAM address. * Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition. * Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition. * Cycle 4: The selected device starts to drive DQ[71:0]. * Cycles 5 to 6: The selected device continues to drive DQ[71:0]. * Cycle 7: The selected device continues to drive DQ[71:0] and drives an SRAM Read cycle. * Cycle 8: The selected device drives ACK from Z to low. * Cycle 9: The selected device drives ACK to high. * Cycle 10: The selected device drives ACK from high to low. At the end of cycle 10, the selected device floats ACK in a three-state condition.
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CYNSE70128
BHI[2] SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70128s Block 0 (devices 0-7) BHO[1] BHO[0] BHO[2]
SRAM
BHI[2] BHI[1] BHI[0] GND Block of 8 CYNSE70128s Block 1 (devices 8-15) BHO[2] BHO[1] BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70128s Block 2 (devices 16-23) BHO[2] BHO[1] BHO[0]
DQ[71:0] CMD[10:0], CMDV
BHI[2] BHI[1] BHI[0] Block of 7 CYNSE70128s Block 3 (devices 24-30) BHO[2] BHO[1] BHO[0]
Figure 12-5. Table of 31 Devices Made of Four Blocks
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CYNSE70128
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ OE_L WE_L CE_L ALE_L z z z z z z z z DQ driven by the selected CYNSE70128 1 0 0 Address z z z Read 00 AB Address
SADR[23:0] ACK SSV SSF
z z
0
1
0
TLSZ = 10, HLAT = 010, LRAM = 0, LDEV = 0.
Figure 12-6. SRAM Read Through Device Number 0 in a Block of 31 Devices (Device Number 0 Timing)
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CYNSE70128
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ OE_L WE_L CE_L ALE_L SADR[23:0] ACK SSV SSF z 0 0 0 1 1 1 z z z z 1 1 1 Read 00 AB Address
TLSZ = 10, HLAT = 010, LRAM = 1, LDEV = 1. Figure 12-7. SRAM Read Through Device Number 0 in a Block of 31 Devices (Device Number 30 Timing)
12.6
SRAM Write with a Table of One Device
SRAM Write enables Write access to the off-chip SRAM that contains associative data. The latency from the second cycle of the Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend on the TLSZ value parameter programmed in the device configuration register. The following explains the SRAM Write operation accomplished with a table of only one device of the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 12-8 shows the timing diagram. For the following description the selected device refers to the only device in the table as it is the only device that will be accessed. * Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write because burst Writes into the SRAM are not supported. * Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0], using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set to 10 to select the SRAM address. Note. CMD[2] must be set to 0 for SRAM Write because burst Writes into the SRAM are not supported. * Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. * Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. At the end of cycle 3, a new command can begin. The Write is a pipelined operation. The Write cycle appears at the SRAM bus, however, with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
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CYNSE70128
cycle 1 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] Write A B x x 1 0 0 0 Address cycle 2 cycle 3 cycle 4 cycle 5 cycle 6
DQ OE_L WE_L CE_L ALE_L SADR 0 1 1 1 z
Address
x
ACK SSV SSF
z 0 0
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1. Figure 12-8. SRAM Write Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
12.7
SRAM Write with a Table of up to Eight Devices
The following explains the SRAM Write operation done through a table(s) of up to eight devices with the following parameters (TLSZ = 01). The diagram of such a table is shown in Figure 12-9. The following assumes that SRAM access is done through CYNSE70128 device number 0. Figure 12-10 and Figure 12-11 show the timing diagram for device number 0 and device number 7, respectively. * Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write because burst Writes into the SRAM are not supported. * Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set to 10 to select the SRAM address. Note. CMD[2] must be set to 0 for SRAM Write because burst Writes into the SRAM are not supported. * Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. * Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. At the end of cycle 3, a new command can begin. The Write is a pipelined operation. The Write cycle appears at the SRAM bus, however, with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
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CYNSE70128
SRAM BHI[2:0] LHO[1] SSF, SSV 6 5 4
CYNSE70128 #0
3 LHI
2
1
0 LHO[0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #1
3 LHI
2
1 LHO[0]
0
DQ[71:0] CMDV CMD[10:0]
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #2
3 LHI
2 LHO[0]
1
0
BHI[2:0] LHO[1]
6
5
4
CYNSE70128 #3
3 2 LHI LHO[0]
1
0
BHI[2:0]
6
5
CYNSE70128 #4
3 LHI LHO[0]
4
2
1
0
BHI[2:0] 3
21 LHI
0
LHI CYNSE70128 #5 LHO[0]
6
5
4
BHI[2:0] 3
2 1 LHI
0
6 LHO[0]
CYNSE70128 #6
5 4 LHI
BHI[2:0]3
2
1 LHI
0
6
CYNSE70128 #7
54 LHI
BHO[0] BHO[1] BHO[2] LHO[1] LHO[0]
BHO[0] BHO[1] BHO[2]
Figure 12-9. Table of a Block of Eight Devices
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CYNSE70128
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ OE_L WE_L CE_L ALE_L z z z z z z z z 0 0 0 Address z z z z Write 01 AB Address x x z
SADR[23:0] ACK SSV SSF
TLSZ = 01, HLAT = XXX, LRAM = 0, LDEV = 0. Figure 12-10. SRAM Write Through Device Number 0 in a Block of Eight Devices
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CYNSE70128
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ OE_L WE_L CE_L ALE_L 1 SADR[23:0] ACK SSV SSF z 0 0 0 1 1 Write 01 AB Address x x 1 z z z z 0 1 1 1
TLSZ = 01, HLAT = XXX, LRAM = 1, LDEV = 1. Figure 12-11. SRAM Write Timing for Device Number 7 in a Block of Eight Devices
12.8
SRAM Write with Table(s) of up to 31 Devices
The following explains the SRAM Write operation done through a table(s) of up to 31 devices with the following parameters (TLSZ = 10). The diagram of such table(s) is shown in Figure 12-12. The following assumes that SRAM access is done through CYNSE70128 device number 0--device 0 is the selected device. Figure 12-13 and Figure 12-14 show the timing diagram for device number 0 and device number 30, respectively. * Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write because burst Writes into the SRAM are not supported. * Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with DQ[20:19] set to 10 to select the SRAM address. Note. CMD[2] must be set to 0 for SRAM Write because burst Writes into the SRAM are not supported. * Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. * Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70128 device. At the end of cycle 3, a new command can begin. The Write is a pipelined operation. The Write cycle appears at the SRAM bus, however, with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
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CYNSE70128
BHI[2] SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70128s Block 0 (devices 0-7) BHO[1] BHO[0] BHO[2]
SRAM
BHI[2] BHI[1] BHI[0] GND Block of 8 CYNSE70128s Block 1 (devices 8-15) BHO[2] BHO[1] BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70128s Block 2 (devices 16-23) BHO[2] BHO[1] BHO[0]
BHI[2] BHI[1] BHI[0] Block of 7 CYNSE70128s Block 3 (devices 24-30) DQ[71:0] BHO[2] BHO[1] BHO[0] CMD[10:0], CMDV
Figure 12-12. Table of 31 Devices (Four Blocks)
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CYNSE70128
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ OE_L WE_L CE_L ALE_L z z z z z z z z 0 0 0 Address Write 01 AB Address x x z z z z z
SADR[23:0] ACK SSV SSF
TLSZ = 10, HLAT = XXX, LRAM = 0, LDEV = 0. Figure 12-13. SRAM Write Through Device Number 0 in a Bank of 31 Devices (Device 0 Timing)
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CYNSE70128
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle 1 2 3 4 5 6 7 8 9 10 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ OE_L WE_L CE_L ALE_L SADR[23:0] ACK SSV SSF z 0 0 0 1 1 1 Write 01 AB Address x x 1 z z z z 1 1 1
TLSZ = 10, HLAT = XXX, LRAM = 1, LDEV = 1. Figure 12-14. SRAM Write Through Device Number 0 in a Bank of 31 CYNSE70128 Devices (Device Number 30 Timing)
12.9
Timing Sequences for Back-to-Back Operations
Table 12-2 shows the idle cycle requirements between operations. The operations in the second column represent operations already performed, and the operations in the first row are those we would like to perform next. Example calculations: 1. Read after Write: The Write takes two 2 cycles, and one 1 idle cycle is required. Thus if the Write is issued in cycle 1, the Read cannot be issued until cycle 4. Note, all cycles after an SRAM Read or an NSE Read (blocking) operation are considered blocked until the ACK signal is returned. 2. x72 Search after Read: The Read command can be issued in 1 cycle after which 5 idle cycles are required before issuing any other command. Thus if the Read is issued in cycle 1, the Search cannot be issued until cycle 7.
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CYNSE70128
Table 12-2. Required Idle Cycles Between Commands
# of Cycles x72/x144 = 1 Cycle x288 = 2 Cycles 1 Cycle 2 Cycles x72/x144 = 1 Cycle 1 Cycle 1 Cycles
OPERATIONS SEARCH READ WRITE LEARN
SEARCH No Wait 5 1 1
READ No Wait / (2 + TLSZ) 13 5 1 1
WRITE No Wait 5 1 1
LEARN No Wait 5 1 1
SRAM TLSZ /(TLSZ + HLAT) 14 5 1 1
SRAM READ 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT 5+TLSZ+HLAT SRAM WRITE 2 2 2 2 2
Notes: 13. When the register being read is SSR/SRR and it matches the target location of the previous search, a READ operation cannot be issued for 2+TLSZ idle cycles to avoid reading the old value. Otherwise there is no idle cycle requirement. 14. The SRAM operation needs to insert idle cycles to avoid SADR bus contention with previous SEARCH.
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CYNSE70128
13.0 Power
CYNSE70128 has two separate power supplies, one for the core (VDD) and another for the I/Os (VDDQ).
13.1
Power-up Sequence
Proper power-up sequence is required to correctly initialize the Cypress NSEs before functional access to the device can begin. RST_L and TRST_L should be held low before the power supplies ramp-up. RST_L must be set low for a duration of time afterward and then set high. The following steps describe the proper power-up sequence. 1. Set RST_L and TRST_L low. 2. Power up VDD, VDDQ and start running CLK1X when operating in CLK1X mode or CLK2X and PHS_L when operating in CLK2X mode. The order in which these signals (including VDD and VDDQ) are applied is not critical. 3. RST_L should be held low for 0.5ms (PLL lock time requirement). In CLK1X mode, the counting starts on the first rising edge of CLK1X after both VDD and VDDQ have reached their steady state voltages. In CLK2X mode, the counting starts on the first rising edge of CLK2X when PHS_L is high, after both VDD and VDDQ have reached their steady state voltages. 4. Continue to hold RST_L low for a minimum of 32 CLK1X cycles (when operating in CLK1X mode) or 64 CLK2X cycles (when operating in CLK2X mode). Set RST_L to high afterward to complete the power-up sequence. For JTAG reset, TRST_L can be brought high after VDD and VDDQ have both reached their steady state voltages. 5. PHS_L does not need to be running during the reset. Also if JTAG is not used, TRST_L does not need to transition HIGH but instead can be held low. Figure 13-1 and Figure 13-2 illustrate the proper sequences of the power-up operation VDD VDDQ CLK2x PHS_L TRST_L RST_L PLL lock time, 0.5ms 64 CLK2x cycles
Figure 13-1. Power-up Sequence (CLK2x)
VDD VDDQ CLK1x TRST_L RST_L PLL lock time, 0.5ms 64 CLK2x cycles
Figure 13-2. Power-up Sequence (CLK1x) Document #: 38-02040 Rev. *F Page 122 of 137
CYNSE70128
13.2 Power Consumption
Figure 13-3 depicts expected power consumption over a range of frequencies. The calculations assume 100% of the operations will be SEARCH operations. If an application includes other operations such as READ or WRITE, then power consumption will be lower. The worst case line indicates power consumption when the I/Os switch 100% of the time. The other lines (All Search Hit and All Search Miss) assume the I/Os switch 50% of the time. Power Consumption of CYNSE70128
1 2
1 0
Absolute Worst Case (75C) All Searches Miss (75C) All Searches Hit (75C)
8
Power (W)
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
Frequency (MHz) Figure 13-3. Power Consumption of CYNSE70128
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CYNSE70128
14.0 Application
Figure 14-1 shows how an NSE subsystem can be formed using a host ASIC and an CYNSE70128 bank. It also shows how this NSE subsystem is integrated in a switch or router. The CYNSE70128 can access synchronous and asynchronous SRAMs by allowing the host ASIC to set the same HLAT parameter in all NSEs within a bank of NSEs.
AM k SR an B
am gr r y ro mo Pe M
ch ar ne S e ngi E
Syst em B
us
t os H SIC A
hr itc so Sw ces o Pr
h itc ic Sw abr F
Net w
or k
Line
In te
r fa c
es
Figure 14-1. Sample Switch/Router Using the CYNSE70128 Device
15.0
JTAG (1149.1) Testing
The CYNSE70128 supports the Test Access Port and Boundary Scan Architecture as specified in the IEEE JTAG standard number 1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and TRST_L. Table 15-1 describes the operations that the test access port controller supports, and Table 15-2 describes the TAP Device ID Register. Note. To disable JTAG functionality, connect the TCK, TMS and TDI pins to VDDQ through a pull-up, and TRST_L to ground through a pull-down. Table 15-1. Supported Operations Instruction Type Description SAMPLE/PRELOAD Mandatory This operation loads the values of signals going to and from I/O pins into the boundary scan shift register to provide a snapshot of the normal functional operation. EXTEST BYPASS IDCODE CLAMP HighZ Mandatory This operation uses boundary scan values shifted in from TAP to test connectivity external to the device. Mandatory This operation loads a single bit shift register between TDI and TDO and provides a minimumlength serial path when no test operation is required Optional Optional Optional This operation selects the Identification register between TDI and TDO and allows the "idcode" to be read serially through TDO. This operation drives preset values onto the outputs of devices. This operation leaves the device output pins in a high-impedance state.
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CYNSE70128
Table 15-2. TAP Device ID Register Field Revision Range Initial Value Description Revision Number. This is the current device revision number. Numbers start from 1 and increment by 1 for each revision of the device. Manufacturer ID. This field is the same as the manufacturer ID used in the TAP controller. Least significant bit. [31:28] 0001
Part Number [27:12] 0000 0000 0000 0100 This is the part number for the device. MFID LSB [11:1] [0] 000_1101_1100 1
16.0
Electrical Specifications
This section describes the electrical specifications, capacitance, operating conditions, DC characteristics, and AC timing parameters for the CYNSE70128, as shown in Table 16-1 and Table 16-2. Table 16-1. DC Electrical Characteristics for CYNSE70128 Parameter ILI ILO VIL VIH VIL VIH VOL VOH VOL VOH IDD2 IDD2 IDD2 IDD2 IDD2 IDD2 IDDl IDDl IDDl Description Input leakage current Output leakage current Input low voltage (VDDQ = 3.3V) Input high voltage (VDDQ = 3.3V) Input low voltage (VDDQ = 2.5V) Input high voltage (VDDQ = 2.5V) Output low voltage (VDDQ = 3.3V) Output high voltage (VDDQ = 3.3V) Output low voltage (VDDQ = 2.5V) Output high voltage (VDDQ = 2.5V) 3.3V supply current at VDD Max 3.3V supply current at VDD Max 3.3V supply current at VDD Max 2.5V supply current at VDD Max 2.5V supply current at VDD Max 2.5V supply current at VDD Max 1.65V supply current at VDD Max 1.5V supply current at VDD Max 1.5V supply current at VDD Max Parameter CIN COUT
Notes: 15. f = 1 MHz, VIN = 0 V. 16. f = 1 MHz, VOUT = 0 V.
Test Condition VDDQ = VDDQ Max, VIN= 0 to VDDQ Max VDDQ = VDDQ Max, VIN=0 to VDDQ Max
Min. -10 -10 -0.3 2.0 -0.3 1.7
Max. 10 10 0.8 VDDQ + 0.3 0.7 VDDQ + 0.3 0.4
Unit
mA mA
V V V V V V V V mA mA mA mA mA mA A A A
VDDQ = VDDQ Min, IOL = 16mA VDDQ = VDDQ Min, IOH = 8mA VDDQ = VDDQ Min, IOL = 8mA VDDQ = VDDQ Min, IOH = 8mA 100 MHz search rate, lOUT = 0mA 83 MHz search rate, lOUT = 0mA 66 MHz search rate, lOUT = 0mA 100 MHz search rate, lOUT = 0mA 83 MHz search rate, lOUT = 0mA 66 MHz search rate, lOUT = 0mA 100 MHz search rate 83 MHz search rate 66 MHz search rate Description Max. 6 6 2.0 2.4
0.4 350 300 240 350 300 240 6.0 5.0 4.0 Unit pF[15] pF[16]
Input capacitance Output capacitance
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Table 16-2. Operating Conditions for CYNSE70128 Parameter VDDQ VDDQ VDD VIH VIH VIL VIL tA tA Description Operating voltage for I/O (3.3V) Operating voltage for I/O (2.5V) Operating supply voltage Input high voltage[17] (3.3V) Input high voltage[17] (2.5V) Input low voltage
[18]
Min. 3.1 2.375 1.425 (for CLK1X = 83 MHz) 1.568 (for CLK1X = 100 MHz) 2.0 1.7 -0.3 -0.3 0 -40 -5
Max. 3.5 2.625 1.575 (for CLK1X = 83 MHz) 1.733 (for CLK1X = 100 MHz) VDDQ + 0.3 VDDQ + 0.3 0.8 0.7 +70 +85 +5
Unit V V V V V V V
C C
(3.3V)
Input low voltage[18] (2.5)V Ambient operating temperature (Commercial) Ambient operating temperature (Industrial) Supply voltage tolerance
%
17.0
AC Timing Waveforms
Table 17-1 and Table 17-2 show the AC timing parameters for the CYNSE70128 device; Table 17-3 shows the same parameters but for 2.5V. Table 17-1. AC Timing Parameters with CLK2X CYNSE70128 CYNSE70128 CYNSE70128 -66 -83 -100 (VDDQ = 3.3V, (VDDQ = 3.3V, (VDDQ = 3.3V, 2.5V) 2.5V) 2.5V) (VDD = 1.5V) (VDD = 1.5V) (VDD = 1.65V) Row Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 fCLOCK tCLOK tCKHI tCKLO tISCH tIHCH tICSCH tICHCH tCKHOV tCKHDV tCKHDZ tCKHSV tCKHSHZ CLK2X frequency. PLL lock time. CLK2X high pulse.[19] CLK2X low pulse.[19]
[19]
Description
Min. 40 3.0 3.0 2.5 Commercial Industrial edge.[19] 0.6 0.8 4.2 2.0
Max. 133 0.5
Min. 40 2.4 2.4 1.8 0.6 0.8 3.5 2.0
Max. 166 0.5
Min. 40 2.0 2.0 1.5 0.5 3.0 2.0
Max. Unit 200 0.5 MHz ms ns ns ns ns ns ns ns 6.5 7.0 ns ns ns ns ns ns
Input set-up time to CLK2X rising edge.[19] Input hold time to CLK2X rising edge.
Cascaded input set-up time to CLK2X rising
Cascaded input hold time to CLK2X rising edge.[19] Rising edge of CLK2X to LHO, FULO, BHO, FULL valid.[20] Rising edge of CLK2X to DQ valid.[20] Rising edge of CLK2X to DQ high-Z.[21] Rising edge of CLK2X to SRAM bus valid.
[20]
8.5 9.0 0.5 0.5 7.0 8.5 9.0 6.5 0.5 6.5 0.5
7.0 7.5 7.0 7.5 6.0 0.5 6.0 0.5
6.5 7.0 5.5
Rising edge of CLK2X to SRAM bus high-Z.[21] low-Z.[21]
14 tCKHSLZ Rising edge of CLK2X to SRAM bus Notes: 17. Maximum allowable applies to overshoot only (VDDQ is 2.5 V supply). 18. Minimum allowable applies to undershoot only. 19. Values are based on 50% signal levels. 20. Based on an AC load of CL = 30 pF (see Figure 17-1, Figure 17-2, and Figure 17-3). 21. These parameters are sampled but not 100% tested, and are based on an AC load of 5 pF.
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Table 17-2. AC Timing Parameters with CLK1X CYNSE70128 CYNSE70128 CYNSE70128 -066 -083 -100 (VDDQ = 3.3V, (VDDQ = 3.3V, (VDDQ = 3.3V, 2.5V) 2.5V) 2.5V) (VDD = 1.5V) (VDD = 1.5V) (VDD = 1.65V) Row Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 fCLOCK tCLOK tCKHI tCKLO tISCH tIHCH tICSCH tICHCH tCKHOV tCKHDV tCKHDZ tCKHSV tCKHSHZ tCKHSLZ CLK1X frequency. PLL lock time. CLK1X high pulse.
[22]
Description
Min. 20 6.75 6.75
Max. 66 0.5
Min. 20 5.4 5.4 1.8 0.6 0.9 3.5 2.0
Max. 83 0.5
Min. 20 4.5 4.5 1.5 0.5 3.0 2.0
Max. Unit 100 0.5 MHz ms ns ns ns ns ns ns ns 6.5 7.0 ns ns ns ns ns ns
CLK1X low pulse.[22] Input set-up time to CLK1X edge.
[22]
2.5 Commercial Industrial 0.6 0.9 4.2 2.0 8.5 9.0 0.5 0.5 7.0 8.5 9.0 6.5
Input hold time to CLK1X edge.[22]
Cascaded input set-up time to CLK1X rising edge.[22] Cascaded input hold time to CLK1X rising Rising edge of CLK1X to DQ valid.[23] valid.[23] low-Z.[24] edge.[22] Rising edge of CLK1X to LHO, FULO, BHO, FULL valid.[23] Rising edge of CLK1X to DQ high-Z.[24] Rising edge of CLK1X to SRAM bus Rising edge of CLK1X to SRAM bus Rising edge of CLK1X to SRAM bus high-Z.[24]
7.0 7.5 0.5 0.5 6.5 7.0 7.5 6.0 0.5 6.0 0.5
6.5 7.0 5.5
Table 17-3. 2.5V AC Table for Test Condition of CYNSE70128 Conditions Input pulse levels (VDDQ = 3.3V) Input pulse levels (VDDQ = 2.5V) Input rise and fall times measured at 0.3V and 2.7V (VDDQ = 3.3V) Input rise and fall times measured at 0.25V and 2.25V (VDDQ = 2.5V) Input timing reference levels (VDDQ = 3.3V) Input timing reference levels (VDDQ = 2.5V) Output reference levels (VDDQ = 3.3V) Output reference levels (VDDQ = 2.5V) Output load
Notes: 22. Values are based on 50% signal levels and a 50%/50% duty cycle of CLK1X. 23. Based on an AC load of CL = 30 pF (see Figure 17-1, Figure 17-2, and Figure 17-3). 24. These parameters are sampled but not 100% tested, and are based on an AC load of 5 pF.
Results GND to 3.0V GND to 2.5V 2 ns see Figure 17-1 2 ns see Figure 17-1 1.5V 1.25 1.5V 1.25V See Figure 17-2 and Figure 17-3
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+2.5V VDDQ = 2.5V / +3.0V VDDQ = 3.3V 90% 10% GND Figure 17-1. Input Wave Form for CYNSE70128 DOUT AC Load Z0 = 50 50 VL = 1.25V for VDDQ = 2.5V VL = 1.5V for VDDQ = 3.3V
90% 10%
CL
Figure 17-2. Output Load for CYNSE70128 VDDQ 208 VDDQ = 2.5V 158 VDDQ = 3.3V Q 192 VDDQ = 2.5V 175 VDDQ = 3.3V 5 pF
For high-Z and VOL/VOH[25, 26] Figure 17-3. I/O Output Load Equivalent for CYNSE70128 Figure 17-4 shows timing waveform diagrams for CLK2X.
25. Output loading is specified with CL = 5 pF, as in Figure 17-3. Transition is measured at 200 mV from steady-state voltage. 26. The load used for VOH, VOL testing is shown in Figure 17-3.
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CYNSE70128
cycle 0 CLK2X cycle 1 cycle 2 cycle cycle 3 4 cycle cycle 5 6 cycle 7 cycle 8 cycle cycle 9 10 cycle 11 cycle 12
CLK Signal Group 0 Signal Group 1 tISCH tIHCH tIHCH
tISCH tISCH
tIHCH Signal Group 2 Signal Group 3 tICSCH
tIHCH tICHCH tCKHOV
tCKHOV tCKHSHZ Signal Group 4
tCKHSV tCKHSLZ tCKHDV tCKHDZ
Signal Group 5
Signal Group 0: PHS_L, RST_L. Signal Group 1: DQ, CMD, CMDV. Signal Group 2: LHI, BHI, FULI. Signal Group 3: LHO, BHO, FULO, FULL. Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV. Signal Group 5: DQ, ACK, EOT. Figure 17-4. AC Timing Waveforms with CLK2X
17.1
Special Note for MULTI_HIT Function on the CYNSE70128
General Description: The CYNSE70128 device provides a "MULTI_HIT" signal as an output. The purpose of this signal is to indicate the occurrence of a multiple hit on a Search in the search engine. Correct Usage: In order to ensure correct function for MULTI_HIT on CYNSE70128: * Backward compatibility mode (with CYNSE70032 and CYNSE70064): Data array bits need to be used as table ID bits. * Non-backward compatibility mode: Either data array bits need to still be used as table ID bits, or the entire data array needs to be configured with one table size. * In multiple NSE configuration (cascaded mode), the "OR" function for the MULTI_HITs from each NSE must be provided externally. The MULTI_HIT signal should be sampled on four CLK1X cycles (or on eight CLK2X cycles) after the issue of the Search command, regardless of the TLSZ and HLAT parameters in the command register.
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CYNSE70128
18.0 Pinout Description
In the following figure and table, the CYNSE70128 device pinout diagram and descriptions are shown (see Figure 18-1 and Table 18-1).
AF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
NC VSS DQ68 DQ66 DQ62 VDDQ DQ56 DQ52 DQ48 VDDQ DQ40 DQ36 DQ34 DQ30 VDDQ DQ24 DQ22 DQ14 VDDQ DQ08 DQ04 DQ02 SSV SSF CMD10 CMD9
AF
VSS VSS DQ70 VDDQ DQ64 DQ60 DQ58 DQ54 DQ50 DQ44 DQ42 DQ38 VDDQ DQ32 DQ28 DQ26 VDDQ DQ18 DQ12 DQ10 DQ06 VDDQ DQ00 VDDQ VSS VSS
AE
RST_L VDDQ VDD VDD VDD VDD VDD NC VDDQ DQ46 VDD VDD VDD VDD VDD VDD DQ20 DQ16 NC VDD VDD VDD VDD VDD CMD8 CMD7
AD
VSS EOT VDD VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VDD CMD6 VDDQ
AC
FULL ACK VDD VSS
FULO1 VDDQ VDD VSS
FULI6 FULO0 VDD VSS
VDDQ FULI5 NC VSS
FULI2 FULI3 FULI4 VSS
FULI0 VDDQ FULI1 VSS
BHO2 VSS VDD VDD
VDDQ BHO1 VDD VDD
BHO0 MULTI_HIT VDD VDD
BHI1 BHI2 VDD VDD
VDDQ BHI0 VDD VDD
LHO0 LHO1 VDD VDD
LHI6 LHI4 LHI5 VSS
LHI2 LHI3 VDDQ VSS
LHI0 LHI1 NC VSS
ID3 ID4 VDD VSS
ID1 ID2 VDD VSS
ID0 VDDQ VDD VSS
TRST _L TDO VDD VSS VSS VSS VSS VSS VSS VSS
TCK TMS VDD VDD VDD VDD VDD NC DQ49 VDDQ VDD VDD VDD VDD VDD VDD DQ19 DQ13 NC VDD VDD VDD VDD VDD
TDI VSS DQ69 DQ65 DQ61 DQ59 DQ55 VDDQ DQ47 DQ45 DQ39 VDDQ DQ33 DQ29 DQ27 DQ23 VDDQ DQ15 DQ11 DQ07 VDDQ DQ01 VSS CFG_L VSS SADR0 0
B
VDD DQ71 VDDQ DQ67 DQ63 VDDQ DQ57 DQ53 DQ51 DQ43 DQ41 DQ37 DQ35 DQ31 VDDQ DQ25 DQ21 DQ17 VDDQ DQ09 DQ05 DQ03 VSS VDDQ HIGH_SPEE D VDD
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS
VSS VDD CMD5 CMD4
AB
VSS VDD CMD3 CMD2
AA
VSS VDD CMD1 CMD0
Y
VSS NC CMDV ALE_L
W
VSS CE_L VDDQ WE_L
V
VSS OE_L PHS_L CLK1X/ CLK2X
U
VDD VDD CLK_MODE SADR23
T
VDD VDD SADR22 VDDQ
R
VDD VDD SADR21 SADR20
P
VDD VDD SADR19 SADR18
N
VDD VDD VDDQ SADR17
M
VDD VDD SADR15 SADR16
L
VSS SADR13 VDDQ SADR14
K
VSS SADR11 SADR12
VSS NC VDDQ
VSS VDD
VSS VDD
VSS VDD
VSS VDD
SADR08 SADR06 SADR05 VDDQ
F
SADR SADR0 03 1 VDDQ
C
26
SADR0 SADR10 SADR07 9
J H G
SADR SADR04 02
E D
26
Figure 18-1. Pinout Diagram
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Table 18-1. Pinout Descriptions for Pinout Diagram Package Ball Number A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A26 A3 A4 A5 A6 A7 A8 A9 AA1 AA2 AA23 AA24 AA25 AC4 AC5 AC6 AC7 AC8 AC9 AD1 AD10 AD11 AD12 AD13 AD14 Signal Name VDDQ DQ[43] DQ[41] DQ[37] DQ[35] DQ[31] VDDQ
[27]
Signal Type 2.5V/3.3V I/O I/O I/O I/O I/O 2.5V/3.3V I/O I/O I/O 2.5V/3.3V I/O I/O I/O I/O Ground 2.5V/3.3V Input 2.5V/3.3V 2.5V/3.3V I/O I/O 2.5V/3.3V I/O I/O I/O Output-T 2.5V/3.3V Ground 1.5V/1.65V Input Ground Ground Ground Ground Ground Ground Input I/O 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V
Package Ball Number AA26 AA3 AA4 AB1 AB2 AB23 AB24 AB25 AB26 AB3 AB4 AC1 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC2 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC3 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE2 AE20
Signal Name CMD[2] VDD VSS FULL ACK VSS VDD CMD[5] CMD[4] VDD VSS VSS VSS VDD VDD VDD VDD VDD VDD VSS VSS VSS EOT VSS VSS VSS VSS VDD CMD[6] VDDQ VDD DQ[44] DQ[42] DQ[38] VDDQ DQ[32] DQ[28] DQ[26] VDDQ DQ[18] DQ[12] VSS DQ[10]
Signal Type Input 1.5V/1.65V Ground Output-T Output-T Ground 1.5V/1.65V Input Input 1.5V/1.65V Ground Ground Ground 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V Ground Ground Ground Output-T Ground Ground Ground Ground 1.5V/1.65V Input 2.5V/3.3V 1.5V/1.65V I/O I/O I/O 2.5V/3.3V I/O I/O I/O 2.5V/3.3V I/O I/O Ground I/O Page 131 of 137
DQ[25] DQ[21] DQ[17] VDDQ DQ[71] DQ[09] DQ[05] DQ[03] VSS VDDQ HIGH_SPEED VDDQ VDDQ DQ[67] DQ[63] VDDQ DQ[57] DQ[53] DQ[51] FULO[1] VDDQ VSS VDD CMD[3] VSS VSS VSS VSS VSS VSS RST_L DQ[46] VDD VDD VDD VDD
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Table 18-1. Pinout Descriptions for Pinout Diagram (continued) Package Ball Number AD15 AD16 AD17 AD18 AD19 AD2 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AE1 AF17 AF18 AF19 AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF3 AF4 AF5 AF6 AF7 AF8 AF9 B1 B10 B11 B12 Signal Name VDD VDD DQ[20] DQ[16] NC VDDQ VDD VDD VDD VDD VDD CMD[8] CMD[7] VDD VDD VDD VDD VDD NC VDDQ VSS DQ[22] DQ[14] VDDQ VSS DQ[08] DQ[04] DQ[02] SSV SSF CMD[10] CMD[9] DQ[68] DQ[66] DQ[62] VDDQ DQ[56] DQ[52] DQ[48] TDI DQ[45] DQ[39] VDDQ Signal Type 1.5V/1.65V 1.5V/1.65V I/O I/O No Connect 2.5V/3.3V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V Input Input 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V No Connect 2.5V/3.3V Ground I/O I/O 2.5V/3.3V Ground I/O I/O I/O Output-T Output-T Input Input I/O I/O I/O 2.5V/3.3V I/O I/O I/O Input I/O I/O 2.5V/3.3V Package Ball Number AE21 AE22 AE23 AE24 AE25 AE26 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AF1 AF10 AF11 AF12 AF13 AF14 AF15 AF16 B23 B24 B25 B26 B3 B4 B5 B6 B7 B8 B9 C1 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 Signal Name DQ[06] VDDQ DQ[00] VDDQ VSS VSS DQ[70] VDDQ DQ[64] DQ[60] DQ[58] DQ[54] DQ[50] NC VDDQ DQ[40] DQ[36] DQ[34] DQ[30] VDDQ DQ[24] VSS CFG_L VSS SADR[00] DQ[69] DQ[65] DQ[61] DQ[59] DQ[55] VDDQ DQ[47] TCK VDDQ VDD VDD VDD VDD VDD VDD DQ[19] DQ[13] NC Signal Type I/O 2.5V/3.3V I/O 2.5V/3.3V Ground Ground I/O 2.5V/3.3V I/O I/O I/O I/O I/O No Connect 2.5V/3.3V I/O I/O I/O I/O 2.5V/3.3V I/O Ground Input Ground Output I/O I/O I/O I/O I/O 2.5V/3.3V I/O Input 2.5V/3.3V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V I/O I/O No Connect
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Table 18-1. Pinout Descriptions for Pinout Diagram (continued) Package Ball Number B13 B14 B15 B16 B17 B18 B19 B2 B20 B21 B22 C6 C7 C8 C9 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D3 D4 D5 D6 D7 D8 D9 E1 E2 Signal Name DQ[33] DQ[29] DQ[27] DQ[23] VDDQ DQ[15] DQ[11] VSS DQ[07] VDDQ DQ[01] VDD VDD NC DQ[49] TRST_L VSS VDD VDD VDD VDD VDD VDD VSS VSS VSS TDO VSS VSS VSS VSS VDD SADR[03] SADR[02] VDD VSS VSS VSS VSS VSS VSS ID[0] VDDQ Signal Type I/O I/O I/O I/O 2.5V/3.3V I/O I/O Ground I/O 2.5V/3.3V I/O 1.5V/1.65V 1.5V/1.65V No Connect I/O Input Ground 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V Ground Ground Ground Output-T Ground Ground Ground Ground 1.5V/1.65V Output Output 1.5V/1.65V Ground Ground Ground Ground Ground Ground Input 2.5V/3.3V Package Ball Number C2 C20 C21 C22 C23 C24 C25 C26 C3 C4 C5 E24 E25 E26 E3 E4 F1 F2 F23 F24 F25 F26 F3 F4 G1 G2 G23 G24 G25 G26 G3 G4 H1 H2 H23 H24 H25 H26 H3 H4 J1 J2 J23 Signal Name TMS VDD VDD VDD VDD VDD SADR[01] VDDQ VDD VDD VDD VDD SADR[05] SADR[04] VDD VSS ID[1] ID[2] VSS VDD SADR[06] VDDQ VDD VSS ID[3] ID[4] VSS VDD SADR[08] SADR[07] VDD VSS LHI[0] LHI[1] VSS NC VDDQ SADR[09] NC VSS LHI[2] LHI[3] VSS Signal Type Input 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V Output 2.5V/3.3V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V 1.5V/1.65V Output Output 1.5V/1.65V Ground Input Input Ground 1.5V/1.65V Output 2.5V/3.3V 1.5V/1.65V Ground Input Input Ground 1.5V/1.65V Output Output 1.5V/1.65V Ground Input Input Ground No Connect 2.5V/3.3V Output No Connect Ground Input Input Ground
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Table 18-1. Pinout Descriptions for Pinout Diagram (continued) Package Ball Number E23 J25 J26 J3 J4 K1 K2 K23 K24 K25 K26 K3 K4 L1 L11 L12 L13 L14 L15 L16 L2 L23 L24 L25 L26 L3 L4 M1 M11 M12 M13 M14 M15 M16 P3 P4 R1 R11 R12 R13 R14 R15 R16 Signal Name VSS SADR[12] SADR[10] VDDQ VSS LHI[6] LHI[4] VSS SADR[13] VDDQ SADR[14] LHI[5] VSS LHO[0] VSS VSS VSS VSS VSS VSS LHO[1] VDD VDD SADR[15] SADR[16] VDD VDD VDDQ VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VSS VSS VSS VSS VSS VSS Signal Type Ground Output Output 2.5V/3.3V Ground Input Input Ground Output 2.5V/3.3V Output Input Ground Output-T Ground Ground Ground Ground Ground Ground Output-T 1.5V/1.65V 1.5V/1.65V Output Output 1.5V/1.65V 1.5V/1.65V 2.5V/3.3V Ground Ground Ground Ground Ground Ground 1.5V/1.65V 1.5V/1.65V 2.5V/3.3V Ground Ground Ground Ground Ground Ground Package Ball Number J24 M2 M23 M24 M25 M26 M3 M4 N1 N11 N12 N13 N14 N15 N16 N2 N23 N24 N25 N26 N3 N4 P1 P11 P12 P13 P14 P15 P16 P2 P23 P24 P25 P26 U24 U25 U26 U3 U4 V1 V2 V23 V24 Signal Name SADR[11] BHI[0] VDD VDD VDDQ SADR[17] VDD VDD BHI[1] VSS VSS VSS VSS VSS VSS BHI[2] VDD VDD SADR[19] SADR[18] VDD VDD BHO[0] VSS VSS VSS VSS VSS VSS MULTI_HIT VDD VDD SADR[21] SADR[20] OE_L PHS_L CLK1X/CLK2X FULI[1] VSS FULI[2] FULI[3] VSS CE_L Signal Type Output Input 1.5V/1.65V 1.5V/1.65V 2.5V/3.3V Output 1.5V/1.65V 1.5V/1.65V Input Ground Ground Ground Ground Ground Ground Input 1.5V/1.65V 1.5V/1.65V Output Output 1.5V/1.65V 1.5V/1.65V Output-T Ground Ground Ground Ground Ground Ground Output-T 1.5V/1.65V 1.5V/1.65V Output Output Output-T Input Input Input Ground Input Input Ground Output-T
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CYNSE70128
Table 18-1. Pinout Descriptions for Pinout Diagram (continued) Package Ball Number R2 R23 R24 R25 R26 R3 R4 T1 T11 T12 T13 T14 T15 T16 T2 T23 T24 T25 T26 T3 T4 U1 U2 U23 Signal Name BHO[1] VDD VDD SADR[22] VDDQ VDD VDD BHO[2] VSS VSS VSS VSS VSS VSS VSS VDD VDD CLK_MODE SADR[23] VDD VDD FULI[0] VDDQ VSS Signal Type Output-T 1.5V/1.65V 1.5V/1.65V Output 2.5V/3.3V 1.5V/1.65V 1.5V/1.65V Output-T Ground Ground Ground Ground Ground Ground Ground 1.5V/1.65V 1.5V/1.65V Input Output 1.5V/1.65V 1.5V/1.65V Input 2.5V/3.3V Ground Package Ball Number V25 V26 V3 V4 W1 W2 W23 W24 W25 W26 W3 W4 Y1 Y2 Y23 Y24 Y25 Y26 Y3 Y4 Signal Name VDDQ WE_L FULI[4] VSS VDDQ FULI[5] VSS NC CMDV ALE_L NC VSS FULI[6] FULO[0] VSS VDD CMD[1] CMD[0] VDD VSS Signal Type 2.5V/3.3V Output-T Input Ground 2.5V/3.3V Input Ground No Connect Input Output-T No Connect Ground Input Output-T Ground 1.5V/1.65V Input Input 1.5V/1.65V Ground
19.0
Ordering Information
Table 19-1 provides ordering information. Table 19-1. Ordering Information Part Number CYNSE70128-66BGC CYNSE70128-66BGI CYNSE70128-83BGC CYNSE70128-83BGI CYNSE70128-100BGC Description NSE NSE NSE NSE NSE I/O Voltage 2.5V/3.3V 2.5V/3.3V 2.5V/3.3V 2.5V/3.3V 2.5V/3.3V Frequency 66 MHz 66 MHz 83 MHz 83 MHz 100 MHz Temperature Range Commercial Industrial Commercial Industrial Commercial
Note: 27. All VDDQ pins should be set to 2.5V or 3.3V (CYNSE70128).
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYNSE70128
20.0 Package Diagram
51-85103-*C
Figure 20-1. 388-lead Ball Grid Array (35 x 35 x 2.33 mm) BG388 APT is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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CYNSE70128
Document History Page
Document Title: CYNSE70128 Network Search Engine Document Number: 38-02040 Orig. of REV. ECN NO. Issue Date Change Description of Change ** *A 111436 116609 01/29/02 08/28/02 AFX OOR New Data Sheet Updated AC Timing, DC Char, JTAG, Pinout Diagram and Pinout Description. Removed references to TEST signals from Pinout Diagram, Pinout Description and Signal Description. Added Power section covering power-up sequence and power consumption. Removed all references to 1.8V I/O. Removed all references to CLK_TUNE[3:0] and set it to 100% ("1001"). Added availability of 66- and 83-MHz Industrial parts. Removed CLK1X power-up sequence diagrams. Added Note to power-up sequence instructions. Added operating temperature range of Industrial parts. Added Minimum Output Data Hold (tCKHDZ and tCKHSHZ) of 0.5 ns. Changed Cascaded Input Hold Time (tICHCH) to 2.0 ns. Corrected Pinout Signal Name for AE26, AF2: VDD to VSS. Added Industrial parts ordering information. Removed Alternative power-up sequence instructions: TOC, Figure 13-3. Added 3.3V to the I/O Voltage of CYNSE70128-83BGI ordering information. Corrected Section 10.6.10 Figure Number Reference from Figure 12-37 to Figure 10-71. Corrected Section 10.6.10 Figure Number Reference from Figure 12-38 to Figure 10-72. Changed Cascaded Input Hold Time (tICHCH) to 2.0ns. Changed Input Hold Time to CLK1X edge (tIHCH) for CYNSE70128-66 to 0.6 ns. Changed Input Hold Time to CLK1X edge (tIHCH) for CYNSE70128-83 to 0.6 ns. Changed Input Hold Time to CLK1X edge (tIHCH) for CYNSE70128-100 to 0.5 ns. Added Input Hold Time to CLK2X edge (tIHCH) AC characteristic for Industrial parts. Added Input Hold Time to CLK1X edge (tIHCH) AC characteristic for Industrial parts. Updated Figure 13-1 on page 122 to reflect the correct waveforms. Also corrected the power-up sequence above the figure. Corrected the pin description of AE26 in the pin assignment table. The description is changed to "ground." Clarified description of HIGH_SPEED pin. Amended Learn description to include restriction at >83 MHz. Modified Section 3.1 Modified Figure 5-1 Added explanation in Section 5.0 Changed Section 10.5 on parallel write Added point 5 in Section 13.1 Power-up sequence Added Section 12.9 and Table 12-2 about idle cycle between successive operations.
*B
119295
12/16/02
ED
*C
123794
02/20/03
KOS
*D
126021
05/08/03
ITL
*E *F
127445 313477
06/25/03 See ECN
DCU AOG
Document #: 38-02040 Rev. *F
Page 137 of 137

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